Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set RTC clock source to the internal 32 KHz LPO. Currently RTC clock is
used to source RTC counter and FTM counter.
Fixes#71289
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Copy the DMA channel information to both UART and SPI
instances of the Flexcomm as only one of them can be
active.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
CSS was deprecated from the mcu-sdk. Removing driver from lpc55s36
to clear build error.
This is a temporary patch to remove the build error.
Fixes#69961
Signed-off-by: David Leach <david.leach@nxp.com>
Add EDMA channels for LPUART RX and TX to LPFLEXCOMM 2 and 4, as these
nodes are enabled with the UART driver
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle
mode). Add DT description and power api implementations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
"RW pinctrl" is clearly SOC specific naming for an IP
that is not necessarily constrained to live on one SOC series.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The pit had a few warnings about
the format of the register address
being uppser case and one of the
reg index values were incorrect.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Enabled the PIT and Multi channel support
for some of the rtXXXX devices.
- rt1010
- rt1060
- rt1160
- rt1170
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Updating the nxp,pit driver to support mutliple
channels. Updating the dts and board overlays
to account for the changes.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
On HAL RTD version 1.0.0, there is available Canexcel_Ip_DeactivateMD()
API that have similar capabilities as can_nxp_s32_abort_msg() API,
can use to instead.
Remove the reg grp_ctrl and reg base_dsc_ctrl that unused
after implementation this.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add FlexSPI clock source to RT1010 devicetree definition for FlexSPI
node, to match FlexSPI clock source defined on standard FlexSPI dt node
that is removed in the RT1010 devicetree.
Fixes#68488
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Setup rx-clock-source for XIP flash. When running from RAM, the FLEXSPI2
attached SIP flash will be reconfigured, so we must ensure the
configuration used for it is valid.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add definition of the DMIC to the RT5xx devicetree, including all
PDM channels.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
A 1KHz counter is present in the LPC RTC.
Add support for this counter to get better
resolution for certain applications.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
