Commit graph

694 commits

Author SHA1 Message Date
Jamie McCrae 97e04aefb8 CODEOWNERS: Add Laird Connectivity Pinnacle 100 codeowner
Assign @rerikson1 as codeowner of Pinnacle 100 board

Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2022-03-24 11:47:11 +01:00
Jamie McCrae 5ba3efb0e2 CODEOWNERS: Add codeowner for Laird Connectivity BL* modules
Add myself as codeowner for BL* modules

Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2022-03-24 11:47:11 +01:00
Jordan Yates 80e7ad7a23 entropy: bt_hci: driver added
Adds an entropy driver that uses Bluetooth HCI commands as its source
of randomness. As this method is blocking, the ISR API is not supported.

As this method will range from relatively slow (same core Bluetooth HCI
controller) to extremely slow (UART HCI Bluetooth controller), use the
xoshiro PRNG by default for RNG generation.

Implements #37186

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-03-23 13:38:47 +01:00
Andrei-Edward Popa 8645de581e drivers: added file structure for Reset Controller Driver
added needed files for reset controller driver

Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
2022-03-23 12:51:39 +01:00
Dylan Hung a24ab24322 soc: arm: Add Aspeed ast10x0 series support
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor.  This
processor operates at 200MHz and executes on SRAM.

This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
2022-03-23 12:50:28 +01:00
Stephanos Ioannidis 0fd0b1b899 CODEOWNERS: Add stephanosio as .github codeowner
Add @stephanosio as a codeowner for the GitHub infrastructure-related
files.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-03-18 13:33:12 -04:00
Tim Lin f2c42663b4 ITE: drivers/i2c: I2C driver divided into two compatibles
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-03-17 15:53:34 -05:00
Henrik Brix Andersen 754ed399f9 drivers: can: add CAN transceiver device driver API
Add API for controlling the state of a CAN transceiver.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-03-15 14:32:29 -05:00
Henrik Brix Andersen 5e8399f84b devicetree: add devicetree/can.h
This contains accessor macros for getting the maximum bitrate supported
by a CAN controller/transceiver combination.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-03-15 14:32:29 -05:00
Immo Birnbaum ec16d571ff CODEOWNERS: add owner for Xilinx PS GPIO controller driver
Add code ownership for the Xilinx Processor System MIO / EMIO GPIO
controller driver.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-03-15 08:44:46 -07:00
Yong Cong Sin 74a0ae01bc shell: Add MQTT backend
Add MQTT backed for shell module.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2022-03-15 10:01:12 +01:00
Peng Fan 01002a3c8d nxp: imx: support i.MX8MP EVK board
Support i.MX8MP EVK A53 with/without jailhouse hypervisor
 - Add dts/dtsi
 - Add board file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan d1b8743b37 drivers: console: add jailhouse debug console
Support jailhouse hypervisor debug console

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-10 14:05:00 -05:00
Peng Fan 8bfdb6ad5e CODEOWNERS: update CODEOWNERS for i.MX8MM
Update CODEOWNERS for i.MX8MM

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-09 09:56:12 -06:00
Sam Hurst 6458649137 stm32: Add STM32 USB TCPC Driver
This commit adds a USB Type-C Port Controller Driver for
the STM32 USB Type-C / USB Power Delivery (UCPD) peripheral

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2022-03-08 11:08:43 +01:00
Dominik Ermel 92109e1f62 doc/guides/device_mgmt: SMP protocol documentation
The commit adds guide that describes format of SMP reqests/responses
as issued by Zephyr implementation within mcumgr.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-03-07 16:45:52 +01:00
Julien Massot c91cb0ce7e MAINTAINERS: add maintainers for Renesas R-Car platform
Update codeowners.
Add maintainers.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-03-03 07:46:24 -05:00
Henrik Brix Andersen bfb2471e59 CODEOWNERS: add myself as additional codeowner for CAN
Add myself as additional codeowner for the various CAN driver and
subsystem components.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-03-02 10:03:46 -08:00
Andy Ross 7e9e993796 CODEOWNERS: Add ipm_cavs_host
New driver needs owners (hijack the earlier cAVS wildcard for the
intra-DSP, it's now a legacy thing and essentially unrelated, but is
for the same platform).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-03-01 09:59:15 -05:00
Jan Van Winkel 94960f72c3 CODEOWNERS: Removed vanwinkeljan
Removed vanwinkeljan as codeowner from:
 * drivers/display
 * dts/posix
 * include/drivers/display.h
 * include/display
 * lib/gui
 * samples/subsys/display
 * samples/drivers/display
 * subsys/cpp
 * subsys/debug/asan_hacks.c
 * subsys/fs/fuse_fs_access.c

Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
2022-02-21 22:14:15 -05:00
Tom Burdick 1e9ada4eb9 dma: cavs: Add gpdma derivative of dw dma for cavs
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-02-21 20:59:08 -05:00
Yuriy Vynnychek a8619169c4 drivers: pinmux: remove Telink B91 driver
Removed Telink B91 driver since it is replaced by Pincrl.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-02-21 19:41:44 -05:00
Torsten Rasmussen ea082ac2c9 cmake: only write devicetree files when there are changes.
As part of #40167 is was discovered that devicetree headers are always
generated when CMake re-runs.

This causes all source files that directly or indirectly through
included headers to recompile when CMake re-runs, even if there are no
changes to devicetree.

This commits introduces `zephyr_file_copy(...)` similar to
`file(COPY_FILE ...)` from CMake 3.21.
However, as CMake 3.20 is supported by Zephyr we need a zephyr variant
of this function to allow usage with CMake 3.20.

This ensures that only when there are changes to devicetree headers,
then source files will recompile.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2022-02-11 15:47:09 +01:00
Thomas Ebert Hansen 07193f04c3 codeowners: Add Bluetooth controller tests
Add Bluetooth controller tests directory and set it to Bluetooth
controller maintainer (cvinayak) and the Bluethooth controller LLCP
refactoring team.

Signed-off-by: Thomas Ebert Hansen <thoh@oticon.com>
2022-02-04 11:23:05 +01:00
Yonatan Schachter 3266e82055 boards: Added support for the Raspberry Pi Pico board
Added support for Raspberry Pi's Pico board, using
the RP2040 SoC.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter a2aa02dbc8 drivers: gpio: Added support for raspberry pi
Added GPIO support for the RP2040 SoC. Only one
core is supported.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter cd7bd5f450 drivers: serial: Added support for raspberry pi
Added a serial driver for the RP2040. Only polling
API is supported.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter fd59038312 drivers: pinctrl: Added pinctrl driver for RPi Pico
Added a pinctrl driver for the Raspberry Pi Pico series

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter db5b2780bf soc: Added support for Raspberry Pi's RP2040 SoC
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2022-02-02 16:23:35 +01:00
Torsten Rasmussen c8ddc34bb8 scripts: generate image info header file
This commit adds the `gen_image_info.py` script which supports creation
of a header file with image information from the EFL file.

This version populates the header file with:
- Number of segments in the image
- LMA address of each segment
- VMA address of each segment
- Size of each segment

The header file can be used by a secondary build system which needs this
information.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2022-01-22 16:57:31 -05:00
Antony Pavlov 05b9bde34a boards: mips: add Qemu Malta support
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.

See https://www.linux-mips.org/wiki/MIPS_Malta for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-19 13:48:21 -05:00
Antony Pavlov 76769a42d0 soc: mips: add Qemu Malta support
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.

See https://www.linux-mips.org/wiki/MIPS_Malta for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
2022-01-19 13:48:21 -05:00
Antony Pavlov 9175ed8244 timer: add support for MIPS CP0 timer
This commit adds a kernel device driver for the MIPS CP0 timer.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-19 13:48:21 -05:00
Antony Pavlov 0369998e61 arch: add MIPS architecture support
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.

This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-19 13:48:21 -05:00
Flavio Ceolin 9dfbde980b codeowners: Add power domains to the list
Add power domains directory and set it to myself.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-01-19 13:35:32 -05:00
Daniel Leung 11c3b1d379 drivers: mm: add skeleton build files and common funcs
This adds skeleton Kconfig/CMakeLists.txt and common implementation
of some sys_mm_drv_*() functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00
Anas Nashif c025abd035 ci: remove .buildkite
We do not use buildkite since 11/2021. Remove the folder with buildkite
specific files.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-01-18 13:24:42 -05:00
Yasushi SHOJI 91970adb75 boards: Add Space Cubics OBC Module 1
This is a single board computer for spacecraft OBC (On-board Computer).
It has a Xilinx FPGA with Cortex ARM M3 core with peripherals, UART, CAN
and others.

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
2022-01-18 13:21:50 -05:00
Gerard Marull-Paretas 412c051fbf codeowners: add GD32 RISC-V boards
Add myself as a code owner for GD32 RISC-V boards.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Jakub Rzeszutko f37f8a5dd5 CODEOWNERS: update getopt library location
Getopt has been moved from /lib/utils to /lib/posix hence
CODEOWNERS must be updated accordingly.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2022-01-06 21:26:59 +01:00
Immo Birnbaum 10c046ce25 CODEOWNERS: owner for SoC Zynq-7000, board qemu_cortex_a9
Set code ownership for:
- soc/arm/xilinx_zynq7000
- boards/arm/qemu_cortex_a9

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-01-06 11:52:27 -05:00
Lukasz Majewski 23ca8d403a CODEOWNERS: Add entry for stm32 QSPI driver
I would like to add myself (@lmajewski) as the code owner for
stm32's QSPI driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-01-04 20:47:29 -05:00
Anas Nashif 0fe74a3f9f MAINTAINER: change microchip maintainer
Change maintainer from scottwcpg to jvasanth1

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-01-04 18:41:05 -05:00
Sylvio Alves 0bebdd9f21 CODEOWNERS: Add myself for ESP32 BT HCI driver
Add myself as codeowner for the ESP32 bluetooth HCI driver

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-04 09:08:19 -05:00
Krzysztof Chruscinski a2802d96a2 CODEOWNERS: Adding ztress codeowner
Adding nordic-krch as ztress codeowner.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-01-01 07:37:22 -05:00
Lingao Meng 422728e156 CODEOWNERS: Add LingaoM for bbc_microbit_v2 board
Add myself as codeowner for the bbc_microbit_v2 driver

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
2021-12-24 20:56:29 -05:00
Dominik Ermel ca1cda28f0 CODEOWNERS: Add myself for mgmt/mcumgr/lib
Add myself as codeowner for the mcumgr library.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2021-12-23 11:18:36 +01:00
Nicolas Pitre faa0b2a848 net: introduce a network packet filter framework
This provides the infrastructure to create network packet filter rules
and to apply them to the RX and TX packet paths. Rules are made of
simple condition tests that can be linked together, creating a facility
similarly to the Linux iptables functionality.

A couple of generic and Ethernet-specific condition tests are also
provided.

Additional tests can be easily created on top of this.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-12-21 17:06:35 +01:00
TOKITA Hiroshi 5c7a0ef888 drivers: interrupt-controller: add Nuclei ECLIC driver
Add support for the ECLIC interrupt controller
which is used with the Nuclei processor core.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi c21bc77169 boards: riscv: Add SiPeed Longan Nano platform
SiPeed Longan Nano is a minimal development board
based on GigaDevice's RISC-V processor.
There are 2 board variations.

longan_nano:      GDGD32VF103CBT6 (128K Flash/32K SRAM)
longan_nano_lite: GDGD32VF103C8T6 ( 64K Flash/20K SRAM)

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00