Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit moves TFM CMakeLists.txt into Zephyr and relocates the
Kconfig.tfm file under the modules/tfm folder.
Updates the manifest to point to related TFM changes.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This patch implements a service that adds multiendpoint
capabilities to RPMsg. Multiple endpoints are intended to be used
when multiple modules need services from a remote processor. Each
module may register one or more RPMsg endpoints.
The implementation separates backend from the service, what
allows to extend this module to support other topologies like
Linux <-> Zephyr.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This script is essentially a Python rewrite of the CMake code we're
using to print boards in cmake/boards.cmake, plus some extra features.
Having this in Python will simplify some later adjustments to our
'usage' build system target in ways that will make its output easier
to read, while simultaneously making 'west boards' more useful.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This is a follow-up to commit 1c89837e79.
Update the path to dfu_usb.c after the file was moved, to prevent
compliance checks from failing because of non-existing file listed
in CODEOWNERS.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
I've been working on ESP WiFi drivers for some time now, so I would like
to help review new patches.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This reverts commit cabbd916cf.
This is considered to be useful enough that it should be restored
as a stable Zephyr API.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This adds a sample application for testing
the LiteX clock control driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
The SAM4L have a unique I2C driver. It shares simultaneously pins for
both master and slave controllers. Each controller have their own
instance. This introduces the TWIM controller that handles only the
master part.
The TWIM controller uses no copy and the driver was prepared to work
with both 7 and 10 bits address. The controller can handler up to 256
bytes for a single transfer allowing long data communication with
almost no CPU intervention.
The driver was wrote specifically to Zephyr. It receives a transfer
list of from upper layers to a specific device on the bus. It programs
the first and second transfer, if it exists, before start. At end of
full read/write interrupt, will program the next data block. This
process repeats until all transfers be executed. The driver uses
interrupt from TWIM to check for erros or program next tranfer.
Future work can enable low power mode on the driver allowing long
transfers with low power consumption.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This change adds support for DNS Service Discovery (DNS-SD)
as described in RFC 6763.
Fixes#29099
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Introduce TagoIO IoT Cloud HTTP post client example. This explorer
Zephyr network resources to demonstrate an end to end application.
The TagoIO allows that any user can test on a easy way Ethernet, WIFI
and Modem (PPP) with BSD sockets. The example provides overlays to
configure WIFI and Modem.
The application consists an a pseudo temperature sensor that sends
periodically data to TagoIO IoT Cloud platform. The data can be
visualized on a web browser dashboard, cellphone or tablet. The
steps to configure TagoIO are described on the example documentation.
Special Variables:
- CONFIG_TAGOIO_DEVICE_TOKEN DEVID token generated by TagoIO
- CONFIG_TAGOIO_HTTP_WIFI_SSID SSID when using WIFI
- CONFIG_TAGOIO_HTTP_WIFI_PSK PASSWD when using WIFI
- CONFIG_MODEM_GSM_UART_NAME UART label when using MODEM
- CONFIG_MODEM_GSM_APN APN when using MODEM
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Inventek es-WIFI modules shield. This shield exposes es-WIFI driver
using Arduino Uno R3 header by UART or SPI interfaces. It shows how
user can create their own overlay and expose es-WIFI driver.
The current Inventek's EVB doesn't have all pins necessary to control
the module by Arduino hearder. This shows how to wire to get ISM43xx
EVB working.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add uart bus interface to extended esWIFI driver. This enables all
Inventek modules with IWIN AT Commands firmware.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This change reworks the cc13xx_cc26xx IEEE 802.15.4 driver to use
the TI RF driver API that is available in modules/hal/ti.
There are a number of benefits to using TI's API including
- a stable multi-OS vendor library and API
- API compatibility with the rest of the SimpleLink SDK and SoC family
- potential multi-protocol & multi-client radio operation
(e.g. both 15.4 and BLE)
- coexistence support with other chipsets via gpio
- vetted TI RF driver resources, such as
- the radio command queue
- highly tuned / coupled RTC & RAT (RAdio Timer) API
Fixes#26312
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
This provides structure for the regulator device hierarchy and a
driver for GPIO-controlled regulators along with its binding.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Adding myself @jenmwms and @aasthagr as codeowners for
/arch/x86/, /soc/x86/, /boards/x86/, and
/drivers/serial/*ns16550* for x86 development.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Move the devicetree bindings for Analog-to-Digital Converters (ADCs)
from dts/bindings/iio/adc to dts/bindings/adc as Zephyr does not have
an IIO layer.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
In early Zephyr days, STM32 code base greatly benefited from the care
of a handful of people.
These days are gone and so did these few people that haven't been
contributing for at least a year now.
CODEOWNERS file is updated to reflect current status of contribution,
for the areas where the is an active contributor.
Let them be thank for these initial contributions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add timing functions and APIs. This is now used with some of the tests
we have for performance and metrics and will be used whereever timing
informations are needed, for example for tracing, profiling and other
operations where timing info is critical.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a generic host command handler framework that allows users to
declare new host command handlers with the HOST_COMMAND_HANDLER macro
at build time. The framework will handle incoming messages from the
host command peripheral device and forwards the incoming data to the
appropriate host command handler, which is looked up by id.
The framework will also send the response from the handler back to the
host command peripheral device. The device handles sending the data on
the physical bus.
This type of host command communication is typically done on an embedded
controller for a notebook or computer. The host would be the main
application processor (aka AP, CPU, SoC).
Signed-off-by: Jett Rink <jettrink@google.com>
The host command peripheral device API abstracts how an embedded
controller sends and receives data from a host on a bus. Each bus like
eSPI, SPI, or I2C would implement their own host command peripheral
device. Each hardware device would then handle the necessary hardware
access to send and receive data over that bus.
The chosen host command peripheral device will be used by the host
command handler framework to send and receive host data correctly.
Signed-off-by: Jett Rink <jettrink@google.com>
@ulfalizer hasn't been active for several months, remove him and add
@mbolivar-nordic. We can add @ulfalizer back if he comes back to the
project.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
At present this test uses an EEPROM emulator. Reuse the same test to
also use the real Atmel AT2x driver and an AT24 emulator, via the I2C
emulation controller.
EEPROM reads and writes for eeprom1 go through the AT2x driver, which
converts them to I2C transactions, which are passed through to the
AT24 emulator for processing. This approach makes more use of 'real'
code, in this case the Atmel AT2x driver.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an emulation controller which routes I2C traffic to attached
emulators depending on the I2C address selected. This allows drivers
for I2C peripherals to be tested on systems that don't have that
peripheral attached, with the emulator handling the I2C traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Create a header file and implementation for emulators. Set up a linker
list so that emulators can be found and initialised at start-up.
Emulators are used to emulate hardware devices, to support testing of
various subsystems. For example, it is possible to write an emulator
for an I2C compass such that it appears on the I2C bus and can be used
just like a real hardware device.
Emulators often implement special features for testing. For example a
compass may support returning bogus data if the I2C bus speed is too
high, or may return invalid measurements if calibration has not yet
been completed. This allows for testing that high-level code can
handle these situations correctly. Test coverage can therefore
approach 100% if all failure conditions are emulated.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Simon Glass <sjg@chromium.org>
The FaZe board can be found in the Seagate FireCuda Gaming SSD devices.
A NVMe SSD and two chips are embedded: an ASMedia ASM2364 USB-to-PCIe
bridge controller and a NXP LPC11U67 MCU. The former is handling the USB
type-C to SSD I/Os while the latter is dedicated to the LED effects. The
two chips are connected together through I2C and GPIOs.
This Zephyr port is running on the LPC11U67 MCU.
Here is a list of the devices connected to the LPC11U67 on a FaZe board:
- ASMedia ASM2364 USB-to-PCIe bridge (I2C master on port O)
- 6 RGB LEDs connected connected to a TI LP5030 LED controller
(I2C device on port 1)
- 1 white LED (SSD activity blinking)
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This adds a very primitive coredump mechanism under subsys/debug
where during fatal error, register and memory content can be
dumped to coredump backend. One such backend utilizing log
module for output is included. Once the coredump log is converted
to a binary file, it can be used with the ELF output file as
inputs to an overly simplified implementation of a GDB server.
This GDB server can be attached via the target remote command of
GDB and will be serving register and memory content. This allows
using GDB to examine stack and memory where the fatal error
occurred.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Sort entries alphabetically and cleanup top level menu for each
subsystem. Move stats subsystem Kconfig from debug into its own Kconfig.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.
This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add myself (@cbsiddharth) as code owner for subsys/mgmt/osdp/,
samples/sybsys/mgmt/osdp/ and includes/mgmt/osdp.h.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
Zephyr introduced subsys/mgmt folder for MCU management. Move UpdateHub
sample to its correspondent folder at sample/subsys/mgmt folder.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Zephyr introduced subsys/mgmt folder for MCU management. Move UpdateHub
to this newly and dedicated space.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
In order to be able to add more entries under 'subsys/mgmt', move the
current contents of it, which relate exclusively to MCUMgr, to its own
folder.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add @abrodkin to the list of CODEOWNERS for ARC code (ARCH,
BOARDS, DTS) instead of @vonhust.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add an entry in CODEOWNERS for auto-assigning reviewers
in MAINTAINERS.yml and get_maintainer.py files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
The esp_8266 shield was added without owner on #24710. Add myself as
an owner of esp_8266 shield files.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The Atmel RF2xx module shield is a generic solution to enable any Atmel
AT86RF2xx IEEE 802.15.4 transceiver. This module enables IEEE 802.15.4
RF2xx Zephyr driver.
The Atmel RF2xx module shield enables any board with an Atmel Xplained,
Xplained-Pro, Arduino or MikroBus expansion header to connect to
networks operation with IEEE 802.15.4, OpenThread or any other stack
based on this media type.
The Atmel RF2xx module is configured to allow interoperate with other
medias like Ethernet. User need configure network stack properlly.
Fixes#26259.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Add setup to utilize buildkite for CI purposes:
1. .buildkite/hooks/pre-command:
* Handles getting git checkout setup against upstream repo
* Setup some west module cache (dirs, clean out files & locks)
* init dir for ccache
2. .buildkite/hooks/post-command:
* Report disk usage (meant for possible debugging)
3. .buildkite/pipeline.yml [uses to determine what to do]:
* setup zephyr env vars
* set which docker container to use
(export some local disk caches for git, west modules, and ccache)
* uses plug to general build annotation on failure (junit-annotate)
4. .buildkite/run.sh [ buildkite wrapper to invoke scripts/ci/run.sh ]
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This change enables specific compiler and linker options to be used in
the case that an arch/posix/os.arch.cmake file exists.
Note: os and arch in the above case are evaluations of
CMAKE_HOST_SYSTEM_NAME and CMAKE_HOST_SYSTEM_PROCESSOR.
Otherwise, the existing "generic" compiler and linker flags in
arch/posix/CMakeLists.txt are used.
Additional flags and checks are provided in
arch/posix/Linux.aarch64.cmake.
Added scripts/user_wordsize.py to detect if userspace is 64-bit or
32-bit, which should be consistent with the value of CONFIG_64BIT
for Aarch64 on Linux.
Fixes#24842
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Add a disk access driver for the stm32 sdmmc component. The driver is
based around the stm32 cube HAL and uses the blocking API.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Many chips have only one serial port. When the serial port is occupied
by other devices, there is a lack of a console to output debugging
information. Semihosting can provide a console. The disadvantage of
semihosting is that a debugger must be connected, so it can only be
used for online debugging.
Signed-off-by: ZhongYao Luo <LuoZhongYao@gmail.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Cloned from counter_basic_api with modifications based on DS3231
limitations:
* Only one device tested per board;
* Counter cannot be stopped or started;
* Alarms are serviced by worker thread, so are not invoked from ISR
and require that test thread yield to allow processing (no
k_busy_wait());
* Multiple Alarms test is disabled as documented in test.
Additional tests were added for DS3231-specific API.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.
The basic functionality is exposed as a counter that is always running
at 1 Hz. Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock. This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This commit renames the CAN sample directory name from `CAN` to `can`
to be consistent with others.
Noting that the CAN driver test directory is named `tests/drivers/can`,
we have no excuse for naming the CAN driver sample directory
`samples/drivers/CAN`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
DAC (digital to analog converter) peripheral driver with a generic API
suitable for most MCUs (only basic DAC features considered).
Signed-off-by: Martin Jäger <martin@libre.solar>
Add pinctl support for the SAM UART and SAM USART devices. We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This GitHub account has been disabled for over a year (it was replaced
by a `ricardosalveti` account). Remove from CODEOWNERS.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This sample now supports SMP UDP transport.
Two config overlays have been added for ipv4 and ipv6, respectively.
The sample documentation has been completely revamped to be less
bluetooth focused and more general.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add code owners for nRF UART drivers and the corresponding Kconfig file
so that some reviewers are automatically assigned for these files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
k_poll() for a signal is often desired for notification of completion
of asynchronous operations, but there are APIs where it may be
necessary to invoke "asynchronous" operations from contexts where
sleep is disallowed, or before the kernel has been initialized.
Extract the general notification solution from the on-off service into
a utility that can be used for other APIs.
Also move documentation out to a resource management section.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The resource table is needed by the Linux kernel OS
for a rpmsg generic support, but is also recognised by OpenAMP.
This table allows to add trace based on the RAM console
and to support rpmsg protocol.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Fixes: #23872
Relocating Zephyr Unittest CMake package to ensure that
HINTS ${ZEPHYR_BASE} in
find_package(ZephyrUnittest HINTS ${ZEPHYR_BASE}) works correctly when
the package has not been exported to CMake user package registry.
This ensure that the new package functionality is fully backwards
compatible on systems where the package is not exported and ZEPHYR_BASE
is set.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Add @nandojve, the SAM V71 platform maintainer, as a code owner for
the SAM E70 platform, as these two platforms share the same base and
are practically identical.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Transfer review assignments from SebastianBoe to tejlmand.
Sebastian Bøe's role is being transferred to Torsten
Rasmussen (tejlmand).
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Adding ZephyrConfig.cmake and ZephyrConfigVersion.cmake allows projects
to use find_package to locate Zephyr.
This means that it will be possible to allow users to run CMake without
the need to source zephyr-env.sh or run zephyr-env.cmd.
This is especially useful for IDEs such as Eclipse or SES, where it will
no longer be required to source the above files before launching the
IDE.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit renames the `cortex_r` directory under the AArch32 to
`cortex_a_r`, in preparation for the AArch32 Cortex-A support.
The rationale for this renaming is that the Cortex-A and Cortex-R share
the same base design and the difference between them, other than the
MPU vs. MMU, is minimal.
Since most of the architecture port code and configurations will be
shared between the Cortex-A and Cortex-R architectures, it is
advantageous to have them together in the same directory.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This adds a rather primitive driver for use with the Intra-DSP
Communication (IDC) on the DSP on certain Intel SoCs. The IDC
generates interrupts from one core to another by writing to
certain registers. This is also being utilized as
the scheduler IPI since it can interrupt other cores.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer on some Intel SoC is a timer driven
directly by external oscillator and is external to the CPU
core(s). It is not as fast as the internal core clock, but
provides a common and synchronized counter for all CPU cores
(which is useful for SMP).
This uses the RISCV timer as base as it is using 64-bit
counter.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add @stephanosio as a code-owner for the tests/arch/arm
test suites, so they get auto-assigned in reviews.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds basic testcases for sanitycheck tool using pytest.
Coverage for the sanitycheck tool is obtained using coverage tool.
Instructions are included in the README.md in
scripts/tests/sanitycheck directory.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
This commit introduces boards/deprecated.cmake to allow deprecation
of existing boards, when a board is renamed.
This allows users to still specify the old board name, and let Zephyr
build system to select the new board name.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit reworks the Xilinx TTC timer driver to use the "match" mode
instead of the "interval" mode which counts up to the specified value
and resets to zero.
Using the "match" mode ensures that the timer keeps counting even after
an interrupt is triggered, and facilitates the tickless mode support
implementation.
This also allows `z_timer_cycle_get_32` to return the correct cycle
count when interrupt is locked; thereby, fixing the k_busy_wait hang
issue.
Note that the TTC "match" mode emulation (and tickless timer operation)
is only stable when the QEMU icount mode is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Since we already have similarly licensed 3-clause BSD files in the tree,
and in particular in our minimal libc, move the fnmatch functionality
from ext/ to lib/.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
IP ethernet switch board includes K66F MCU from NXP
and Micrel/Microchip KSZ8794CNX switch. Board support
includes basic GPIO LED and common functions.
Switch function needs support either based on DSA or
relative feature in Zephyr which is tracked with issue
22061.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Add entropy driver based on GECKO TRNG module along with device
tree support for EFM32PG and EFR32MG SOCs.
Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
Split up requirements.txt into several files so that CI tools can
utilize/reference the specific requirements-<FOO>.txt they may need
while keep things in sync with the development. This is to reduce
both time and amount of work CI actions due to python package install.
Create the following groupings:
1. BASE - needed to build or create zephyr images
2. BUILD-TEST - need to run compile/build tests
3. DOC - need to build the docs
4. RUN-TEST - need for runtime testing
5. EXTRAS - optional or useful for development/developers workflow
Also tried to add a comment about what or why a given package is being
pulled in for.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This never needed to be put in a separate gperf table.
Privilege mode stacks can be generated by the main
gen_kobject_list.py logic, which we do here.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add Platform Environment Control Interface API
This API defines following calls:
- peci_configure
- peci_enable
- peci_disable
- peci_transaction
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
daor-oti and wopu-ot also want to be added automatically as
reviewers to POSIX arch, native_posix, nrf52_bsim and bsim
related test apps.
(see CODEOWNERS for more info about which each is interested on)
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add @stephanosio as a code owner for the Xilinx ZynqMP platform, which
is used as the primary testing platform for the Cortex-R architecture.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace running west command tests in run_ci.sh with a github workflow.
This provides some benefits in that we can run the west command tests on
multiple python versions and host OSes (linux, mac and windows).
Also have the benefit that the tests are only run on modifications to
files in scripts/west_commands/ or scripts/west-commands.yml.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add script to capture tracing stream data with UART backend. This
script is developed based on pyserial, so install it correctly
before using the script.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
This commits adds GPIO driver for LiteX SoC builder.
Due to the fact that GPIO in LiteX is unidirectional and can be
configured with different pins amount per port, additional entries
were added to the dts file.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Update driver code and board files to use new GPIO configuration flags
such as GPIO_ACTIVE_LOW. Also add implementation of new port_* driver
API.
Tested on external SX1509B breakout board and Thingy:52.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Test that the new port API functions all behave as expected, including
physical vs logical level for input and output as well as masked and
set-based output operations. Also tests the new pin API functions.
For running on real hardware this test now uses a local test-specific
devicetree binding. For build-only tests any platform with a GPIO
alias should be tested.
The new code increases flash requirements so add a filter to exclude
platforms that won't link.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Watchdog type is found on e.g. Pearl/Jade Gecko, often
more than 1 is present.
Driver supports timeout and (minimum) window configuration
and reset or timeout interrupt support for now.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Add a script that sets up Docker networking and starts the net-tools
Docker container. If successful, run Zephyr with native_posix and
execute the appropriate net-tools container executable. The proper
net-tools executable and arguments is selected depending on the
basename of the sample directory. This script needs to be updated
if the net-tools Docker image is updated in some incompatible way.
The net-tools directory is assumed to exist at the same level as
the Zephyr base directory, but its location can be set using the
'-N' command line argument. Likewise, '-Z' sets the Zephyr top level
directory.
When stopping Zephyr, go through all child processes since running a
native posix or other variant of Zephyr may cause a hierarchy of
processes to be created.
Fixes: #19540
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Introduce the basic ARM64 architecture support.
A new CONFIG_ARM64 symbol is introduced for the new architecture and new
cmake / Kconfig files are added to switch between ARM and ARM64.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
ARM cores may have a per-core architected timer, which provides per-cpu
timers, attached to a GIC to deliver its per-processor interrupts via
PPIs. This is the most common case supported by QEMU in the virt
platform.
This patch introduces support for this timer abstracting the way the
timer registers are actually accessed. This is needed because different
architectures (for example ARMv7-R vs ARMv8-A) use different registers
and even the same architecture (ARMv8-A) can actually use different
timers (ELx physical timers vs ELx virtual timers).
So we introduce the common driver here but the actual SoC / architecture
/ board must provide the three helpers (arm_arch_timer_set_compare(),
arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file
imported through the arch/cpu.h header file.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The Silicon Labs EFM32 Jade Gecko MCU includes:
* Cortex-M3 core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* multiple low power peripherals
This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
There are various situations where it's necessary to support turning
devices on or off at runtime, includin power rails, clocks, other
peripherals, and binary device power management. The complexity of
properly managing multiple consumers of a device in a multithreaded
system suggests that a shared implementation is desirable. This
commit provides an API that supports managing on-off resources.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This commit adds initial support for the Silicon Labs EFM32
Giant Gecko GG11 StarterKit.
Features supported for now are NVIC, SysTick, GPIO, Flash,
Counter, I2C, UART and Ethernet. Support for Watchdog and
ADC will follow as soon as their respective PRs are merged.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Add support for storing the CANopen object dictionary to non-volatile
storage.
This fixes#15278.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a Zephyr driver and abstraction layer for use by the 3rd party
CANopenNode module.
CANopenNode depends on the CO_driver.h file for platform-specific type
definitions, locking primitives, and CAN bus driver API.
This fixes#15278.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move LVGL sample from samples/gui/lvgl to samples/display/lvgl to have
a unified location for display related samples.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
As of January 2020, David is no longer working on the Zephyr
documentation, so he should not be automatically added as reviewer.
I've commented out rather than removed the lines so when a replacement
is found, the lines can easily be added back.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add driver for the Texas Instruments LMP90xxx series of multi-channel,
low-power 16-/24-bit sensor analog frontends (AFEs).
The functionality is split into two drivers; an ADC driver and a GPIO
driver.
Tested with LMP90080 and LMP90100.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
PWM driver for LiteX SoC builder was created.
Because LiteX supports only one channel for each PWM device,
an appropriate restriction was made.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This adds I2C bitbang driver for LiteX SoC builder with its bindings.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This adds PRBS ranom number generator driver for
LiteX SoC builder with its bindings.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This adds support for the EC (embedded controller) on a Google
reference board with codename "kukui". This board uses the STM32F098RC
chip. We built an application for the board and verified UART
functionality on the board.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.
There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Pattern being <domain>_<model>.<c/h>.
Here interrupt_controller as a domain would be far too long so
shortening it to "intc", as DTS does actually.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
wdt_install_timeout() was skipped as it installs an ISR-context
callback handler function. The rest are simple wrappers.
Added myself as the maintainer of the syscall handlers. WDT
subsystem appears to not currently have an owner.
Fixes: #21432
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
net/lib/config/ is important generic part of the network stack, and
should be reviewed by the same people as net/lib/. (Besides, I
originally factored out this lib in the first place.)
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Added leak suppression, by implementing __lsan_default_suppressions
function, for SDL2 and X11 library which are used by the SDL display
driver.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
gen_syscall_header.py is not longer necessary, it was just creating a
file including syscall.h. This header is now included directly by
gen_syscalls.py.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Szymon was removed from all Bluetooth paths a while ago, and this is
simply an overlooked leftover.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
/lib/libc/ was listed twice in the file
The first entry was overriden by the 2nd
And so was the case for
/samples/bluetooth/
In this second case, the override lost a user, so add it
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
There were two conflicting entries for sensor samples, which resulted in
the wrong person getting assigned as a reviewer.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add API for accessing Electrically Erasable Programmable Read-Only
Memory (EEPROM) devices.
EEPROMs have an erase block size of 1 byte, a long lifetime, and allows
overwriting data on byte-by-byte access.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This adds supoprt for the Atmel SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Add myself to owner of subsys/logging/log_backend_net.c so
that if there are changes to that file, I get notified.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Add shell commands for setting PWM period and duty cycle (in cycles,
microseconds, or nanoseconds).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
1) Add cryptographically secure random functions to provide
FIPS 140-2 compliant random functions.
2) Add name to random function choice selectors to ease
selection in SOC .defconfig files
3) Add bulk fill random functions.
Signed-off-by: David Leach <david.leach@nxp.com>
Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC.
Based heavily on the existing mcux LPSPI driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Not a top-level zephyr core API and tied to third party environment, so
move it to where the code is in lib/updatehub.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
