Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enabling by default (if SPI3 used) because it affects all revisions
since "Engineering B", including the most recent one as of today
(revision 3).
Size changes when enabled:
- -Og: flash +160 bytes (+0.02%), RAM +8 bytes (+0.01%)
- -Os: flash +144 bytes (+0.02%), no change to RAM usage
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Save FP user register and FP register file during context switch.
This change enables shared FP registers mode using CONFIG_FPU_SHARING.
Since there is no lazy stacking, the FPU registers will be saved regardless
of whether floating point calculations are performed in the threads when
CONFIG_FPU_SHARING is enabled. This require 72 additional bytes in the
stack memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The unaligned trap bit is set by default, contrary to the xmc
reference manual. This PR unsets the bit in the initialization.
It can still be set later via the CONFIG_TRAP_UNALIGNED_ACCESS
option.
Note that the same approach is used in xmc4500 reference software
init code (see SystemCoreSetup() in infineon hal module).
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Cleaning up the instances of CODE_LOCATION used in the soc
clock_init and replaced them with the Kconfig
FLASH_MCUX_FLEXSPI_XIP due to the correlation with
the flexspi clocks and the XIP feature of Flexspi.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added information about pin output direction into
Z_PINCTRL_STM32_PINCFG_INIT if output_low or output_high is provided.
GPIO output flag is set in configuration struct and this will end up
being loaded into MODE register. Because of that it is no longer
required for pinctrl_configure_pins() to set MODE register value for
GPIO input/output.
Fixes#53141.
Signed-off-by: Lukasz Mazur <lukasz.mazur@hidglobal.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
xmc_device.h sets which XMC4xxx.h file to include and also sets
other defines such as GLOCK_GATING_SUPPORTED.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add region calculations and implementation of
sys_mm_drv_query_memory_regions to pass calculated regions down
the line.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This patch makes IMR context save an option that can be enabled. By
default FW, after D3 state transition, will be boot using normal flow.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IT8XXX2 HW support sha256 calculation, and its calculation is
faster than FW. We place SHA256 message, hash and key data
(total 512bytes) in RAM. If we enable hw sha256, because
HW limits, the sha256 data must place in first 4KB of RAM.
We add sections for hw sha256 calculation in linker.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Currently, memory from __rodata_region_end to __kernel_ram_start (or
_app_smem_start if config userspace) was uncovered by programable MPU
region. But to config static MPU region (nocache region is on ths
region), the programable MPU region need confg full patition.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the messaging unit to ensure that the RT11xx dual core mode will
wait for the second core to boot successfully during early init
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx features CM4 core, which must be booted from CM7 core. Add
support for loading an image for the CM4 to RAM, and booting the CM4 core
from this image. Each image is built independently using sysbuild, and the
M4 image build produces built collateral with load address information the
M7 image can use to load it to RAM
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow linking code into OCRAM region when building for RT1xxx SOCs. This
can be used on the RT11xx dual core SOCs as a shared memory region, when
the M7 core needs to load code into a region accessible to the M4 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Low-power management is part of the RTC peripherals' domain
on ESP32C3. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Low-power management is part of the RTC peripherals' domain
on ESP32S2. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
- Adds initial system power management support.
- Adds option to add extra delay when waking from
deep sleep.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Low-power management is part of the RTC peripherals' domain
on ESP32. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Expand ifdef by adding new Kconfig option UDC_KINETIS as
preparation for USBFSOTG UDC driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
