Commit graph

364 commits

Author SHA1 Message Date
Dawid Niedzwiecki ad53863d1a counter: stm32 rtc: improve assigning configs
The config values have been hardcoded as magic values. Introduce
universal calculation based on the DTS entries.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-09-26 15:05:35 +02:00
Manuel Argüelles 45c8cb2343 counter: nxp_pit: use clock control to obtain module's clock rate
Use standard clock control API to retrieve the PIT clock rate instead of
using the HAL.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-22 09:23:30 +02:00
Manuel Argüelles ddaacd9ee8 counter: nxp_pit: allow to specify max load value
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-22 09:23:30 +02:00
Manuel Argüelles f8e16ae81a counter: nxp_pit: support flexible number of interrupts
Depending on the SoC design, the PIT channel interrupts can be
individual or OR'ed together to a single interrupt line.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-22 09:23:30 +02:00
Manuel Argüelles d590fb2f78 counter: nxp_pit: support only top callback
This periodic timer (PIT) has a single load value register for each
channel, which is currently used for both alarm and top callback APIs.
If using both APIs together (which is a valid use-case) it will write
to the same register causing unexpected behavior of the timer.

The nature of the PIT is to trigger an event (like interrupts) at a
certain rate, and not to produce single-shot events. Hence keep only top
callback functionality.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-22 09:23:30 +02:00
Manuel Argüelles e22f634f33 counter: nxp_pit: support multiple instances
Add support for multiple device instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-22 09:23:30 +02:00
Jerzy Kasenberg 0d877e7855 drivers: counter: Fix Smartbond counter get_rate
When timer calibration for SmartBond(tm) was added, opaque type
clock_control_subsystem_t that used to have device tree ordinal
number was changed to enum to allow values that are not in device
tree (like no clock selection).

During this process counter driver for SmartBond(tm) was not updated
accordingly, resulting in wrong frequency being reported to counter
driver.

Failure could be seen when samples/drivers/counter/alarm was execute on
da1469x_dk_pro board.

With this fix counter driver uses correct type when
clock_control_get_rate is called and counter test works again.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2023-09-20 20:17:11 +01:00
Brett Witherspoon 4a250c26b1 drivers: counter: fix index of stm32 RTC source clock
The DT_INST_CLOCKS_CELL macro takes as the first argument the device
instance and not the cell index. This change correctly gets the second
index of the first device as intended.

Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
2023-09-20 11:21:40 +01:00
TOKITA Hiroshi cf242016b4 drivers: counter: Add support for rpi_pico timer
Adds support for rpi_pico timer

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-09-13 16:18:44 +02:00
Nick Ward 2d65acca3a drivers: gpio: use gpio_is_ready_dt helper function
Update `struct gpio_dt_spec` use with gpio_is_ready_dt()

Signed-off-by: Nick Ward <nix.ward@gmail.com>
2023-08-28 08:48:35 -05:00
Daniel Leung 729fd4c574 counter: rename shadow variables
Rename shadow variables found by -Wshadow.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-08-22 11:39:58 +02:00
Balsundar Ponnusamy 8fae16f596 drivers: counter: Add shell commands for timer
add shell implementation for timer

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2023-08-16 10:20:31 +02:00
Balsundar Ponnusamy e3f0ec6d41 drivers: counter: add snps apb timer
adding driver for snps dw timer

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2023-08-16 10:20:31 +02:00
Sreeram Tatapudi b7e623c886 drivers: counter: cat1: Fix formatting issues
Minor format fixes for consistency

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-08-10 08:13:11 +00:00
Sreeram Tatapudi fa471172b7 drivers: counter: cat1: Fix test_single_shot_alarm_notop
TC "test_single_shot_alarm_notop" is failing because there were 2 ISR
callbacks instead of one. this is because of invoking
ifx_cat1_counter_set_int_pending incorrectly. Updated
ifx_cat1_counter_set_alarm to fix this

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-08-10 08:13:11 +00:00
Markus Fuchs 27af62603c drivers: counter: gecko: Add SYSRTC stimer support
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.

This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Maciej Sobkowski 9bc3ee67be drivers: counter: Add Ambiq counter driver
This commit adds Ambiq counter driver for Apollo4p SoCs.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-07 16:12:58 +02:00
Pavlo Havrylyuk f4a1d40924 drivers: counter: Add Infineon CAT1 counter driver
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter

Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
2023-07-26 09:10:31 +02:00
Marek Matej 6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Sean Nyekjaer f21526c5c9 drivers: counter: stm32: void return value from reset_line_toggle_dt
Suggested-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
2023-07-20 10:57:12 +00:00
Erwan Gouriou 32efdf9239 drivers: counter: stm32: Review use const TIM_TypeDef on few series
A recent Cube update moved C0/L1/WBA to use const TIM_TypeDef
Align counter driver implementation.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-07-20 09:20:57 +00:00
Erwan Gouriou feef931fbb drivers: counter: stm32: Use const TIM_TypeDef on stm32f2 series
A recent factorisation moved F2 to non const TIM_TypeDef.
This is an error, move it back to const TIM_TypeDef.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-07-19 14:31:31 +00:00
Kim Bøndergaard 6775b263f3 drivers: counter: stm32_rtc: Make dependent of !RTC
New RTC API seems to conflict with old RTC implementations based on
COUNTER

This scheme follows Zephyrproject-rtos issue 56599 while keeping backward
compatibility.

Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
2023-07-18 11:05:23 +00:00
Erwan Gouriou 829fa5e70a drivers: counter: stm32wba: Avoid warning at build
STM32WBA LL API defines non const TIM_TypeDef.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-07-12 11:48:10 +02:00
Sean Nyekjaer f1d91a24ac drivers: counter: stm32: read clock divider register for stm32mp1 boards
Since clocks aren't declared in the devicetree for the stm32mp1
co-processor. Read the resulting clock divider here instead.

Signed-off-by: Sean Nyekjaer <sean@geanix.com>
2023-07-06 09:44:01 +00:00
Jerzy Kasenberg b896ca5771 drivers: counter: Add Smartbond basic support
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2023-07-05 13:00:50 +02:00
Daniel Leung 26ecaba4af drivers: syscalls: use zephyr_syscall_header
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-06-17 07:57:45 -04:00
Carlo Caione cb11b2e84b barriers: Move __DSB() to the new API
Remove the arch-specific ARM-centric __DSB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Adam Wojasinski 2fb78f7c63 counter: counter_nrfx_rtc: Align to renamed nrfx symbols
New nrfx release brings renamed macros and symbols in nrf_rtc.
This commit alligns RTC counter SHIM to it.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-05-05 11:47:53 +02:00
Anisetti Avinash Krishna bfeb5043ac drivers: rtc: rtc_mc146818: Added RTC driver for Motorola MC146818B
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.

Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.

Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-27 14:15:22 +02:00
Francois Ramu a77851b73e drivers: counter: stm32 timer counter driver LL prototype
Adapt the stm32 counter-timer driver to the stm32_ll function
prototype. Some stm32 families have
LL_TIM_OC_GetCompareCHx(TIM_TypeDef some others have
LL_TIM_OC_GetCompareCHx(const TIM_TypeDef.
This will fix compilation warning.
Adds the macro for stm32L0 16bit timers.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-04-24 13:32:29 +02:00
Gerard Marull-Paretas 09c5f09109 drivers: counter: mcux_qtmr: fix SYS_INIT call signature
Use the new int f(void) SYS_INIT call signature.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-19 07:18:54 -05:00
Gerard Marull-Paretas 1eb683a514 device: remove redundant init functions
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-19 10:00:25 +02:00
Francois Ramu d574636b78 drivers: counter: add the support of the RTC to the stm32h5
Add the stm32h5 serie to the stm32 RTC counter driver
EXTI Line is 17 (for stm32h50x or non-secure stm32h56x/h57x).
The drivers must Enable access to the BackUp Domain.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-04-05 10:39:19 +00:00
Pieter De Gendt 6b532ff43e treewide: Update clock control API usage
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t)

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-04-05 10:55:46 +02:00
Henrik Brix Andersen c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
Gerson Fernando Budke eb2c6d7e2c drivers: timer: sam: Update to use clock control
This update Atmel SAM timer driver to use clock control drivers.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-03-21 14:12:25 -07:00
Krzysztof Chruscinski 656b0e6426 drivers: counter: Adapt to use device tree
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.

Adapting dtsi for all SoCs and adapting test configuration.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2023-03-20 16:59:40 +01:00
Krzysztof Chruscinski 93619d7b73 drivers: counter: nrfx_rtc: Use clock control when driver enabled
RTC shall enabled LF clock only if CLOCK_CONTROL driver is enabled.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2023-03-20 16:49:50 +01:00
Benjamin Björnsson c02688a308 drivers: counter: add support for rtc in STM32C0-series
This commit extends the rtc counter driver to work on
the STM32C0-series.

Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
2023-03-20 09:53:49 +01:00
Benjamin Björnsson 6c8ef27a77 drivers: counter: stm32_rtc: enable backup domain only when supported
The STM32C0-series does not have a backup domain, this patch
enables us to extend this driver to the C0-series.

Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
2023-03-20 09:53:49 +01:00
Rainer Paat ed2c25effc drivers: counter: MCP7940N: initialization fix
This PR fixes MCP7940N initialization failure on Sunday if
external battery is used to keep the RTC running over the
MCU or Zephyr OS restarts.

Signed-off-by: Rainer Paat <rapaat@gmail.com>
2023-03-10 14:09:49 +01:00
Adrian Bonislawski 1243fa7f2d drivers: counter: align ace rtc get_value with api
This will align ace rtc get_value parameter with counter api
and fix build warning

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-02-20 11:13:45 +01:00
Adrian Bonislawski c1b216d3bf drivers: counter: return status in ace rtc counter
This will align return value with counter API and fix build warning

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-02-20 11:13:45 +01:00
Adrian Bonislawski 9952576945 drivers: counter: fix ace counters build errors
This will fix includes and allow to successfully build ace counters

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-02-20 11:13:45 +01:00
Guillaume Gautier 60fc300195 drivers: counter: Do not keep RTC value between resets on STM32
This commit changes the ability to keep the RTC value between resets, and
turns it off by default.
Though this feature makes sense for an RTC counting the time and date,
here it is used as a counter. As such the registers used for coutning
should be reset after each MCU reset.

This change puts back in place the previous behavior before the Kconfig
CONFIG_COUNTER_RTC_STM32_BACKUP_DOMAIN_RESET was removed.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-02-08 12:10:34 +01:00
Adam Kondraciuk dac3a42063 drivers: counter: align to NRF_TIMER hal
Align driver with changes introduced in the hal. `nrf_timer_frequency_set`
was changed to `nrf_timer_prescaler_set`, update driver accordingly.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-06 10:07:17 +01:00
TOKITA Hiroshi c1fc906599 drivers: counter: gd32_timer: Remove is_bit_mask() implementation
Replace is_bit_mask() with IS_BIT_MASK() and remove the implementation.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-01-10 09:23:14 +01:00
TOKITA Hiroshi 33963c43ca drivers: counter: nrfx_timer: Remove is_bit_mask() implementation
Replace is_bit_mask() with IS_BIT_MASK() and remove the implementation.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-01-10 09:23:14 +01:00
TOKITA Hiroshi 21dc3f58e4 drivers: counter: nrfx_rtc: Remove is_bit_mask() implementation
Replace is_bit_mask() with IS_BIT_MASK() and remove the implementation.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-01-10 09:23:14 +01:00