Add a typedef for the row type rather than using uint8_t directly, this
allow supporting bigger matrix as an option by using a different type.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change CROSS_COMPILE_TARGET to be defined based on CONFIG_SOC_SERIES.
This fix adjusts CROSS_COMPILE_TARGET to ensure compatibility
with the 'espressif' toolchain variant, following the changes in
commit 6b57b3b786.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Update the stm32h5xx/drivers/include/
to enable the SAI, DelayBlock and DCACHE only if the instance
exists in the soc. Which is not the case for stm32h503x device
https://github.com/zephyrproject-rtos/hal_stm32/pull/181/
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the "rc" text to include that it can also be returned when
SMP version 2 is used to indicate an SMP error instead of a group
error.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds non-volatile settings for the HAS Server. Those are needed to
restore the client awareness of preset list entries exposed by the
server. Based on the settings, the implementation determines how to
notify the client about the HAS related characteristic value changes.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
When using picolibc before 1.8.5, the only way to get 'long long' support
was to use the full version, including floating point support. This is too
large for this testcase.
Reduce the size of the printf code by switching to the version without
64-bit integer support. This allows the test to pass when using older
picolibc versions, such as that included with SDK version 0.16.3.
Signed-off-by: Keith Packard <keithp@keithp.com>
Regression failure introduced problem where driver code was not properly
wrapping code that only existed when compiled for IPv4/v6 applications.
Fixes#65549
Signed-off-by: David Leach <david.leach@nxp.com>
When using picolibc before 1.8.5, the only way to get 'long long' support
was to use the full version, including floating point support. This is too
large for this testcase.
Reduce the size of the printf code by switching to the version without
64-bit integer support. This allows the test to pass when using older
picolibc versions, such as that included with SDK version 0.16.3.
Signed-off-by: Keith Packard <keithp@keithp.com>
qemu_x86_tiny has very limited memory resources; if too much text is
included in this test, it will not have enough remaining memory to run
it.
When using picolibc before 1.8.5, the only way to get 'long long' support
was to use the full version, including floating point support. This is too
large for this testcase.
Reduce the size of the printf code by switching to the version without
64-bit integer support. This allows the test to pass when using older
picolibc versions, such as that included with SDK version 0.16.3.
Signed-off-by: Keith Packard <keithp@keithp.com>
On some devices such as STM32U5, there is no UART WKUP dedicated registers
as the hardware block has an integrated autonomous wakeup capability.
Hence it's capable to wake up the device from stop modes (down to Stop 1).
This behavior relies on RCC UESM bit which is enabled by default at reset
and not modified today in drivers.
Since driver will not compile otherwise, remain in this simple
configuration. This might be changed later on, if a need is seen to disable
UESM bit.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Added note about the migration steps needed to support the new IGMP api.
The api now expects an additional argument used for joining an IGMPv3
group.
Signed-off-by: Ibe Van de Veire <ibe.vandeveire@basalte.be>
Added igmpv3 support based on the already existing structure for igmpv2.
The already existing api is not modified to prevent breaking exisiting
applications.
Signed-off-by: Ibe Van de Veire <ibe.vandeveire@basalte.be>
Added igmpv3 checksum function to make it possible to calculate the
checksum of a complete igmpv3 pkt at once.
Signed-off-by: Ibe Van de Veire <ibe.vandeveire@basalte.be>
This commit fixes the following compiler warnings:
* implicit declaration of function 'strtoul'; did you mean 'strtok'?
* passing argument 2 of 'parse_named_int' discards 'const' qualifier
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Workaround for DMAT errata was applied on all SoCs declaring STM32U5
DMA compatible.
This errata has been fixed in later SoCs revisions and should not be
applied anymore as this can cause compatibility issues with power mgmt
(can not enter STOP1 in some cases).
Declare a specific Kconfig symbol to restrict the workaround only to the
set of SoCs impacted by the issue and requiring workaround.
Note that I preferred using Kconfig over device tree since it doesn't feel
right to declare a compatible on a silicon bug base.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Andy Ross re-implementation of MMU layer with some subtle changes,
like re-using existent macros, fix page table cache property when
direct mapping it in TLB.
From Andy's original commit message:
This is a reworked MMU layer, sitting cleanly below the page table
handling in the OS. Notable differences from the original work:
+ Significantly smaller code and simpler API (just three functions to
be called from the OS/userspace/ptable layer).
+ Big README-MMU document containing my learnings over the process, so
hopefully fewer people need to go through this in the future.
+ No TLB flushing needed. Clean separation of ASIDs, just requires
that the upper levels match the ASID to the L1 page table page
consistently.
+ Vector mapping is done with a 4k page and not a 4M page, leading to
much more flexibility with hardware memory layout. The original
scheme required that the 4M region containing vecbase be mapped
virtually to a location other than the hardware address, which makes
confusing linkage with call0 and difficult initialization
constraints where the exception vectors run at different addresses
before and after MMU setup (effectively forcing them to be PIC
code).
+ More provably correct initialization, all MMU changes happen in a
single asm block with no memory accesses which would generate a
refill.
Signed-off-by: Andy Ross <andyross@google.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This file doesn't need the asm2 header, and the preprocessor logic
around whether to include the backtrace header is needless (all it
does is declare functions).
Signed-off-by: Andy Ross <andyross@google.com>
Add a Kconfig option (and build warning) alerting about the problem
of the kernel spilling register in behave of the userspace.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add a Kconfig option to tell whether or not using thread
local storage to store current thread.
The function using it can be called from ISR and using
TLS variables in this context may (should ???) not be
allowed
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Use thread local storage to check whether or not a thread is running
in user mode. This allows to use threadptr to properly support tls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Only clear the user stack to 0xAA if CONFIG_INIT_STACKS is
enabled. Otherwise, write 0x00 as if the stack is in BSS.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During arch_kernel_init(), the interrupt stack is being
initialized. However, if the current in-use stack is
the interrupt stack, it would wipe all the data up to
that point in stack, and might result in crash. So skip
initializing the interrupt stack if the current stack
pointer is within the boundary of interrupt stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We need to use the mmu spin lock when invalidating the cache during
tlb shootdown, otherwise it is possible that this happens when another
thread is updating the page tables.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When the target has a cache way size (cache size / cache wasy) bigger
than the page size we have cache aliasing, since the number of bits
required by the cache index is bigger than the number of bits in the page
offset.
To avoid this problem we flush the whole cache on context switch or when
the current page table is changed.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This enables tests/kernel/mem_protect/mem_protect to be tested
on Xtensa.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This test requires architecture specific code to work.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Swap page tables at exit of exception handler if we are going to
be restored to another thread context. Or else we would be using
the outgoing thread's page tables which is not going to work
correctly due to mapping and permissions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When adding a thread to a memory domain, we need to also update
the mapped page table if it is the current running thread on
the same CPU. If it's not on the same CPU, we need to notify
the other CPUs in case the thread is running in one of them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
After changing content of page table(s), it is needed to notify
the other CPUs that the page table(s) have been changed so they
can do the necessary steps to use the updated version. Note that
the actual way to send IPI is SoC specific as Xtensa does not
have a common way to do this at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When kernel OOPS is raised, we need to actually go through
the process of terminating the offending thread, instead of
simply printing the stack and continue running. This change
employs similar mechanism to xtensa_arch_except() to use
illegal instruction to raise hardware exception, and going
through the fatal exception path.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Trigger exception on Xtensa requires kernel privileges. Add
a new syscall that is used when ARCH_EXCEPT is invoked from userspace.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This extracts the printing of fatal exception information into
its own function to declutter xtensa_excint1_c().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There are known exceptions which are not fatal, and we need to
handle them properly by returning to the fixup addresses as
indicated. This adds the code necessary in the exception
handler for this situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
When MMU is enabled, we need some scratch registers to preload
page table entries. So update gen_zsr.py to that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This changes the TLB misses handling back to the assembly
in user exception, and any page faults during TLB misses to be
handled in double exception handler. This should speed up
simple TLB miss handling as we don't have to go all the way to
the C handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add a header with architecture specific macros and
definitions that re used on userspace for stack
objects.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Userspace support for Xtensa architecture using Xtensa MMU.
Some considerations:
- Syscalls are not inline functions like in other architectures because
some compiler issues when using multiple registers to pass parameters
to the syscall. So here we have a function call so we can use
registers as we need.
- TLS is not supported by xcc in xtensa and reading PS register is
a privileged instruction. So, we have to use threadptr to know if a
thread is an user mode thread.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simplify the logic around xtensa_mmu_init.
- Do not have a different path to init part of kernel
- Call xtensa_mmu_init from C
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Replace all autorefill helpers with only one that invalidates both,
DTLB and ITLB, since that is what is really needed.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This is an older driver and didn't support the weak
arch_printk_char_out() hook, which is a link-time symbol that allows
logging to work from the first instruction. Some drivers can't do
that because they need an initialization step, but this one works
great.
Signed-off-by: Andy Ross <andyross@google.com>
This register alias was originally introduced to allow A0 to be used
as a scratch register when handling exceptions from MOVSP
instructions. (It replaced some upstream code from Cadence that
hard-coded EXCSAVE1). Now the MMU code is now using too, and for
exactly the same purpose.
Calling it "ALLOCA" is only confusing. Rename it to make it clear
what it's doing.
Signed-off-by: Andy Ross <andyross@google.com>
