Commit graph

972 commits

Author SHA1 Message Date
Gerard Marull-Paretas c759a35d08 drivers: use DT_INST_ENUM_IDX(_OR) macros
Replace `DT_ENUM_IDX(_OR)(DT_DRV_INST(...),` pattern with
`DT_INST_ENUM_IDX(_OR)(...,`.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-18 19:12:07 -05:00
Tim Lin e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Christopher Friedt 7c6039a1d2 drivers: serial: nrfx: refactor for atomic_t as long
This driver aliases a regular `int` to `atomic_t` but that
should be updated to `long` with the change to `atomic_t`.

Added a comment to highlight that the variable was aliased.

Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
2021-11-15 09:59:01 -05:00
Daniel Leung 40c2b1e99c uart: add API support for wide data
This adds API to support datum more than 8-bit wide. Drivers are
still responsible for the implementation.

Fixes #31914

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-09 19:44:38 -05:00
Francois Ramu cf60639390 drivers: serial: stm32 usart driver clears the RXNE through flag
For some stm32 soc devices, the USART (or UART) flag RXNE is cleared
by the LL_USART_ClearFlag_RXNE function which directly writes
the RXNE bit of the Status register. This is the case with the
stm32F1x, stm32F2x,stm32F4x, stm32L1x.
Some other are using the Rx Data Flushing function.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-09 15:43:48 -05:00
Sylvio Alves b0c48a2182 drivers: uart: esp32: set device to initialize pre-kernel
Uart post kernel initialization does not allow starting shell
properly. This issue was added in UART unifying PR.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-09 15:18:15 -05:00
Francois Ramu 95e2c39497 drivers: uart stm32 flushing Rx register once the RXNE irq is enabled
When the "Read data register not empty" irq occurs,
this commit is cleaning the RXNE flag by flushing the RX register
since the Receive Data Reg. (USART_RDR) has not be read previously
This could be the case when aborting a Rx for example.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-04 09:45:11 -05:00
Julien D'ascenzio 7b21050f19 drivers/uart: stm32: fix a bug during transmission
If a transmission is made with poll_out and immediately after an other
transmission is made with interrupt api the transmission is locked.
We fix this behavior by clearing the tx_poll_stream_on flag during the
irq_tx_enable function

Signed-off-by: Julien D'ascenzio <julien.dascenzio@paratronic.fr>
2021-11-04 07:13:11 -04:00
Gerard Marull-Paretas 811a09bd83 drivers: serial: npcx: drop inline attribute for PM action callback
Making function inline doesn't provide any benefit here, and is
inconsistent with all other definitions.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-03 20:27:18 -04:00
Gerard Marull-Paretas 4baf1e01ff drivers: use common PM action callback naming
The PM callback is no longer referenced as "pm_control" but
"pm_action_cb", so reflect this new naming on the callbacks.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-03 20:27:18 -04:00
Sylvio Alves d5aa5c2a77 drivers: esp32: uart: use hal functions
In order to have Espressif SoCs working with
the same uart drivers, all low level functions
are now replaced to hal_espressif HAL calls.

This also changes pinmux, gpio and uart
init order to meet its dependencies.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-03 16:47:32 -04:00
Felipe Neves 4c069b9894 drivers: serial: add support for esp32c3
into esp32_serial unified driver

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-29 16:09:09 -04:00
Dmytro Firsov d9a3efb834 xenvm: drivers: serial: Implement serial interface to Xen PV console
This commit adds minimal support of Xen hypervisor console via UART-like
driver. Implementation allows to use poll_in/poll_out char interface for
uart_console.c driver directly to HV console instead of using Xen
virtual PL011 UART. Future implementation will support interrupt driven
interface on Xen event channels, currently it is under development.

Also this commit introduces early console_io Xen interface, which allows
to receive printk/stdout messages quickly after start, but requires Xen,
built with CONFIG_DEBUG option.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2021-10-29 15:23:33 +02:00
Immo Birnbaum 811d77a88a drivers: serial: xlnx_xuartps: Fix interrupt-driven operation
Fixes interrupt-driven operation. With the previous way of
handling the TX FIFO and the interrupt flags, the operation
of the UART was prone to stalling when using it as the
console I/O device.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum fe33a24721 drivers: serial: xlnx_xuartps: enable this driver for Zynq-7000 series SoCs
Enable this driver to be used in conjunction with Xilinx Zynq-7000
series SoCs.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Gerson Fernando Budke 45d60c4d4c drivers: serial: Add gd32 uart driver
Introduce minimal serial driver support for gigadevice soc.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-10-28 11:17:25 +02:00
Robert Lubos a2e619ec8b drivers: uart_nrfx_uarte: Use predefined data pointer where applicable
After recent changes in the driver, the predefined `data` pointer in
`uarte_nrfx_pm_control()` would not be used in CONFIG_UART_ASYNC_API
configuration. Fix this by replacing `get_dev_data()` calls with
predefined data pointer where applicable.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-10-25 19:26:43 -04:00
Torsten Rasmussen b87d8e7d7d kconfig: uart: remove experimental on UART_ASYNC_API setting
The setting UART_ASYNC_API is no longer considered experimental.
Also remove `new` from title and help test as the feature no longer can
be considered new.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-10-25 10:46:48 +02:00
Timo Teräs 1eb6831ddd drivers: uart_ns16550: Fix dts hw_flow_control mapping to config
DT_INST_NODE_HAS_PROP() returns true always since the boolean
tag is valid. Use DT_INST_PROP_OR() to get the real value.

Fixes: baecd7e55a drivers: uart_ns16550: Remove CMake-based templating
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
2021-10-20 07:13:42 -04:00
Henrik Brix Andersen d711d224c2 drivers: serial: neorv32: use shared serial driver init priority
Use the shared CONFIG_SERIAL_INIT_PRIORITY for driver initialization
priority.

Override the default value for the NEORV32 SoC to ensure the serial
driver is initialized after the syscon driver by default.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-19 06:44:46 -04:00
Maureen Helm ad1450510a drivers: serial: Refactor drivers to use shared init priority Kconfig
Refactors all of the serial drivers to use a shared driver class
initialization priority configuration, CONFIG_SERIAL_INIT_PRIORITY, to
allow configuring serial drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The one
exception is uart_lpc11u6x.c which previously used
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS.

This change was motivated by an issue on the frdm_k64f board where the
serial driver was incorrectly initialized before the clock control
driver.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-17 10:58:09 -04:00
Henrik Brix Andersen c6ada02210 drivers: serial: add neorv32 uart driver
Add UART driver for the open-source NEORV32 RISC-V compatible processor
system (SoC).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Pavlo Hamov 89e907d4f0 drivers: serial: esp32: Unify serial driver for esp32 & esp32s2
1) Allow use of interrup driven instance.
   ROM implementation could be selected via dts compatiable.

2) Use UART rx fifo and timeout interrupt for end of message detection.
   Added to decrease interrupts count on data reception

3) Use ESP_LL api.

Signed-off-by: Pavlo Hamov <p.hamov@venstar.com>
2021-10-13 10:14:23 -04:00
Krzysztof Chruscinski c590b3545a drivers: serial: Use microseconds to represent timeout
Updated uart_rx_enable() and uart_tx() to use timeout given
in microseconds. Previously argument was given in milliseconds.
However, there are cases when milliseconds granularity is not
enough and can significantly reduce a throughput, e.g. 1ms is
100 bytes at 1Mb.

Updated 4 drivers which implement asynchronous API. Updated
places where API was used.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-10-12 12:26:56 +02:00
Yuriy Vynnychek 1242f5129d drivers: serial: b91: irq_tx_ready update to check TX IRQ
Updated b91_irq_tx_ready API to check TX IRQ enabled.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-10-11 21:02:21 -04:00
Glauber Maroto Ferreira fb1632925e soc: esp32: partial code standardization
Replaces the prefixes of gpio_matrix_in and gpio_matrix_out
to unify those function calls on all supported socs.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-10-10 14:52:41 -04:00
Manojkumar Subramaniam d79d26f1ae drivers: serial: stm32: renable IT RXNE as part of graceful disable
async_rx_disable does not re-anable RXNE interrupt, it was disabled
during async_rx_enable

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2021-10-05 19:19:16 -04:00
Daniel Leung ef0d955758 uart: ns16550: add workaround to re-enable interrupts in ISR
In some configurations (e.g. edge interrupt triggers),
an interruptible event occurs during ISR and the host interrupt
controller does not see the new event due to IIR is constantly
asserting interrupts. For example, the callback handles RX and
then TX. If another character comes in before end of TX processing
(TX interrupt still asserts while raising RX interrupt), the host
interrupt controller may not see this new event. So if needed,
the IER is being toggled to re-assert interrupts at the end of ISR
to nudge the host interrupt controller to fire the ISR again.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-04 20:49:13 -04:00
Dawid Niedzwiecki 1031cfd51e drivers: serial: ns16550: fill full fifo
Put the maximum number of bytes into Tx FIFO in the fill_fifo routine
to reduce CPU usage.

Previously, the THRE bit was checked in a loop, but, according to doc -
"In the FIFO mode, it is set when the XMIT FIFO is empty, and is
cleared when at least one byte is written to XMIT FIFO.", so only one
byte was transferred every interrupt. That was generating a big amount
of interrupts, which consumes CPU time.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-09-28 20:10:00 -04:00
Steven Lemaire cc5f769436 drivers: serial: gecko: add hw flow control support for EFR32 Series 2
Add hardware flow control support for the EFR32MG21 and other modules
using GPIO_USART_ROUTEEN_RTSPEN (and GPIO_USART_ROUTEEN_CTSEN) instead
of the Kconfig SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION.

The driver already contained the section settings the RTS and CTS pins
for modules using the GPIO_USART_ROUTEEN_(RTS|CTS)PEN define, but it was
not compiling because of an #ifdef checking only for
CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION and not both.

Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
2021-09-28 11:39:02 +02:00
Erwan Gouriou 79ff645390 drivers/uart: stm32: Simplify code around pm_constraints handling
Now that we're clearer around pm constraints management in various
TX cases (poll streams, irq driven or async), make some code
simplifications to ease readability.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-09-21 10:47:56 -04:00
Erwan Gouriou a3de3df5dc drivers/uart: stm32: Fix pm_constraint handling
Introduce new logic to set/release pm_constraint during serial TX
transactions.

First change is to introduce an internal flag and utility functions
to control the set/release constraint balancing per uart device.
This way, whatever the mix of transactions or API calls, we
ensure a single uart device can only do 1 or 0 to the PM state
constraint. Constraint can't then be set more than once, released w/o
having been set or released more than it was set.

The last part of the change reworks the triggers for constraints
set/release operations.
In order not to disturb driver operations, if irq driven mode or PM is
enabled, don't enable TC interrupt handling by default.
Instead, map the pm_constraint setting to the way TC flag is handled
in normal mode of operations (irq driven or async).
As a consequence, in irq driven mode, pm_constraint is set/released on
tx_enable/tx_disable api calls, which gives API user full control
on transaction protection vs low power operations.
Finally, we emulate the same behavior on TX poll transaction, by
enabling TC irq at the start of a stream and disabling TC irq once
stream is completed. This is controlled with a dedicated device flag.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-09-21 10:47:56 -04:00
Ron Smith 683dbc4573 drivers: serial: uart_sam0: Fix async tx done event triggering to early.
uart_sam0_dma_tx_done callback triggers when the last byte
is transferred from the tx sram buffer to the sercom DATA register.
However the byte has yet to be transmitted completely which can lead to
incorrect event handling if UART_TX_DONE is expected to signal
the end of transmission.

Signed-off-by: Ron Smith <rockyowl171@gmail.com>
2021-09-19 19:31:25 -04:00
Ron Smith a0d92453d8 drivers: serial: uart_sam0: move err_check methodout of if guard
Fixes a compile error for the err_check function not being found if
if CONFIG_UART_INTERRUPT_DRIVEN is not enabled.

Signed-off-by: Ron Smith <rockyowl171@gmail.com>
2021-09-19 19:31:25 -04:00
Gerard Marull-Paretas a7f13755ed drivers: serial: stm32: remove unnecessary flag clear
According to reference manual, use of TC is "to avoid corrupting the
last transmission when the USART is disabled or enters Halt mode.". It
is safe to remove it since it is not checked when CONFIG_PM=n.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-09-13 17:53:19 -04:00
Gerard Marull-Paretas e3f4907efe drivers: serial: stm32: use PM constraints to prevent suspension
In the current implementation the STM32 UART driver required to enable
`CONFIG_PM_DEVICE` when `CONFIG_PM=y` to function properly. The main
reason is that in some situations, like in polling mode, transmissions
are not fully synchronous. That is, a byte is pushed to the _queue_ if
it is empty and then the function returns without waiting for it to be
transmitted to the wire. This makes sense to make things like per-byte
transmission efficient. However, this introduces a problem: the system
may reach idle state, and so enter low power modes before the UART has
actually finished the last data in the queue. If this happens,
communications can be interrupted or garbage data may be put into the
UART line.

The proposed solution in this patch uses PM constraints to solve this
problem. For the IRQ/DMA case it is easy since we can set the constraint
before transmission start, and when the completion (TC) interrupt is
received we can clear it. However, the polling mode did not have the
capability to signal the completion. For this case, a simpler IRQ
routine is provided to just release the constraint. As a result, the PM
hooks are not required and so system can operate with just `CONFIG_PM`.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-09-13 17:53:19 -04:00
Dawid Niedzwiecki 3e696a0f84 drivers: serial: ns16550: fix uart initialization
Do not set DLAB bit in Line Control Register when the access to
the baud rate divisor registers is not needed.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-09-13 07:06:33 -04:00
Katsuhiro Suzuki 763428d5a4 drivers: serial: sifive: support SiFive Freedom series SoCs
This patch changes condition of 'depends on' of sifive UART driver
to support other SoCs of SiFive Freedom series.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Ron Smith e54d2553f3 drivers: serial: uart_sam0: Correct check for interrupts enabled
Fixes the issue where uart_sam0_irq_tx_ready would return true if
the INTFLAG was set even though the INTSET bit for the given
interrupt was not enabled yet through uart_sam0_irq_tx_enable.

Signed-off-by: Ron Smith <rockyowl171@gmail.com>
2021-09-01 11:50:51 +02:00
Ron Smith 18830991e1 drivers: serial: uart_sam0: Update to correct bitmask
Update uart_sam0_irq_tx_enable to use the correct INTENSET bitmask.

Signed-off-by: Ron Smith <rockyowl171@gmail.com>
2021-09-01 11:50:51 +02:00
Johann Fischer 92a00ee39b drivers: uart_altera_jtag_hal: use DEVICE_DT_INST_DEFINE()
The conversion to devicetree seems to be half lost
for this driver. There are already bindings and nodes for
compatible "altr,jtag-uart", update driver to use it.
Remove last mention of CONFIG_UART_CONSOLE_ON_DEV_NAME.

Resolves #37207

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-08-23 18:53:47 -04:00
Tomasz Bursztyka f70ecc1099 drivers/pcie: Improve and fix MBAR retrieval depending on use cases
So far pcie_get_mbar() has been the only way to retrieve a MBAR. But
it's logic does not fit all uses cases as we will see further.
The meaning of its parameter "index" is not about BAR index but about
a valid Base Address count instead. It's an arbitrary way to index
MBARs unrelated to the actual BAR index.

While this has proven to be just the function we needed so far, this has
not been the case for MSI-X, which one (through BIR info) needs to
access the BAR by their actual index. Same as ivshmem in fact, though
that one did not generate any bug since it never has IO BARs nor 64bits
BARs (so far?).

So:

- renaming existing pcie_get_mbar() to pcie_probe_mbar(), which is a
  more relevant name as it indeed probes the BARs to find the nth valid
  one.
- Introducing a new pcie_get_mbar() which this time really asks for the
  BAR index.
- Applying the change where relevant. So all use pcie_probe_mbar() now
  but MSI-X and ivshmem.

Fixes #37444

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-08-20 06:30:20 -04:00
Yuriy Vynnychek b7f99d4a47 drivers: serial: b91: full duplex mode support
Improved fifo_fill API: stop and return on RX.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-20 06:23:24 -04:00
Francois Ramu 744e1dc692 drivers: serial: stm32 uart defines dma slot with macro
The STM32_DMA_SLOT macro from include/drivers/dma/dma_stm32.h
must be used here, especially for dma of type v2bis.
In this case, the dma-cell is not defined and slot is null.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-08-16 19:35:36 +02:00
Mark Wang 857b8508d0 drivers: serial: NXP: Enable flow control for uart_mcux_lpuart
add flow_ctrl filed and give it initialized value
    based on hw_flow_control.
Initialize mcux lpuart based on flow_ctrl

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2021-08-12 14:49:09 -05:00
Scott Worley ad19104f28 Microchip: MEC172x: Add UART driver
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-08-09 16:21:33 -04:00
Glauber Maroto Ferreira 8e865a7a88 esp32s2: drivers: serial: add minimal uart driver
based on uart rom functions, also enable console driver
on top of this driver, which enables logging

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-08-09 13:03:14 -04:00
Mulin Chao ab87854d9b driver: serial: replace suffix nuvoton with numicro
Replace the suffix "nuvoton" with "numicro" for Nuvoton microcontroller
serial driver.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-08-07 20:37:24 -04:00
Andrzej Głąbek 3842babc79 drivers: serial: nrf: Make pull-ups on UART pins configurable
This is a follow-up to commit 3656ba5ae9.

Do not enforce pull-up resistors to be enabled on RXD and CTS pins
in nRF UART drivers, as in certain hardware designs this may be
undesirable or may even make certain hardware not working.
Instead, provide devicetree properties that allow enabling of those
resistors when it is actually needed.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2021-08-06 19:17:26 -04:00
Gerard Marull-Paretas 7ccc1a41bc pm: use actions for device PM control
Instead of passing target states, use actions for device PM control.
Actions represent better the meaning of the callback argument.
Furthermore, they are more future proof as they can be suitable for
other PM actions that have no direct mapping to a state. If we compare
with Linux, we could have a multi-stage suspend/resume. Such scenario
would not have a good mapping when using target states.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00