Commit graph

53 commits

Author SHA1 Message Date
Marouen Ghodhbane 3fb0e784ff drivers: counter: mcux: add support for TPM
Add TPM native Zephyr driver. It's mainly inspired from the GPT
counter implementation.

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-04-30 08:53:59 +02:00
Emilio Benavente 04b240c830 dts: bindings: renamed binding used for pit
Renamed pit binding from nxp,kinetis-pit
to nxp,pit

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2024-03-07 13:23:58 -06:00
Declan Snyder 31722446aa drivers: counter: Add NXP MRT driver
Add driver for NXP Multirate Timer

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
TOKITA Hiroshi cf242016b4 drivers: counter: Add support for rpi_pico timer
Adds support for rpi_pico timer

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-09-13 16:18:44 +02:00
Balsundar Ponnusamy 8fae16f596 drivers: counter: Add shell commands for timer
add shell implementation for timer

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2023-08-16 10:20:31 +02:00
Balsundar Ponnusamy e3f0ec6d41 drivers: counter: add snps apb timer
adding driver for snps dw timer

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
2023-08-16 10:20:31 +02:00
Maciej Sobkowski 9bc3ee67be drivers: counter: Add Ambiq counter driver
This commit adds Ambiq counter driver for Apollo4p SoCs.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-07 16:12:58 +02:00
Pavlo Havrylyuk f4a1d40924 drivers: counter: Add Infineon CAT1 counter driver
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter

Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
2023-07-26 09:10:31 +02:00
Jerzy Kasenberg b896ca5771 drivers: counter: Add Smartbond basic support
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2023-07-05 13:00:50 +02:00
Henrik Brix Andersen c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
TOKITA Hiroshi 981d88bf7b drivers: counter: add support for GD32 timer
Adds support for GD32 timer

Note: Currently, it is not supporting RISC-V(GD32V) devices.
It needs some work on the interrupt controller first.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
Manuel Arguelles 4fbf940019 drivers: counter: support NXP S32 System Timer Module
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-11-30 11:29:39 +01:00
Piotr Kmiecik 0acd68247f drivers: ace_v1x wallclock driver
Wallclock driver with functionality required by ACE v1x base firmware.

Signed-off-by: Piotr Kmiecik <piotrx.kmiecik@intel.com>
2022-09-06 17:44:03 +02:00
Jimmy Zheng a2cc4b702f drivers: counter: add Andes atcpit100 counter driver
atcpit100 counter driver support 4 32-bit PIT channel, using channel 3 as
the default counter.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-08-26 11:55:36 +02:00
Gerard Marull-Paretas bbda65a99a drivers: counter: increase COUNTER_INIT_PRIORITY
Some counter devices depend on buses (e.g. I2C for Maxim DS3231). Bus
devices are tipically initialized with KERNEL_INIT_PRIORITY_DEVICE as
well, so there's no guarantee counter will be initialized be initialized
before without manually tweaking priorities.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-05 12:55:51 +02:00
Glauber Maroto Ferreira af5310d500 esp32: drivers: counter: update build references
Updates build references of the Counter API
implementation based on Espressif's General
Purpose Timers to differentiate from the one
based on RTC.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-08-04 15:30:18 +02:00
Glauber Maroto Ferreira dbbfcfc22d esp32: driver: counter: add RTC-based implementation
add RTC-based implementation of the counter driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-27 09:48:33 +02:00
Jan Peters 253cec5c95 drivers: counter: add driver for NXP QTMR counters
The driver is implemented using the MCUXpresso SDK.

Signed-off-by: Jan Peters <peters@kt-elektronik.de>
2022-05-03 20:41:23 -05:00
Kent Hall ba37d5935e drivers: counter: Counter API implementation for STM32F4 Series (TIMER).
- Shim for counter API using LL_TIM driver.
- Supports all general-purpose (TIMx) timers.

Signed-off-by: Kent Hall <kjh2166@columbia.edu>
2021-12-11 14:20:17 -05:00
Pieter De Gendt 4d161a3b23 drivers: counter: NXP SNVS rtc: Add support for NXP imx SNVS RTC
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-12-07 09:45:43 -06:00
Maureen Helm 165963c115 drivers: counter: Refactor drivers to use shared init priority
Refactors all of the counter drivers to use a shared driver class
initialization priority configuration, CONFIG_COUNTER_INIT_PRIORITY, to
allow configuring counter drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are the maxim_ds3231 and mcp7940n drivers which have a
dependency on a SPI driver and must therefore initialize later than the
default device priority.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-23 20:44:49 -04:00
Toby Firth 893bfc0fc1 drivers: counter: added ctimer driver for lpcexpresso55s69
Added shim driver for the CTIMERs for the lpcexpresso55s69 board.

Fixes: #22705

Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2021-08-24 17:13:22 -04:00
Kieran Mackey 94e006f0fc drivers: counter: add driver for Microchip MCP7940N RTCC
Microchip MCP7940N is a Real-Time Clock/Calendar. It operates on a I2C
bus. It can be used to set a calendar time and has two alarm channels.
When an alarm is asserted the state of the MPF pin of the MCP7940N will
change (depending on gpio active high/active low setting) to trigger an
interrupt.

Signed-off-by: Kieran Mackey <kieran.mackey@lairdconnect.com>
2021-07-30 19:51:29 -04:00
Piotr Mienkowski 1145986096 drivers: Add Atmel SAM counter (TC) Driver
Add basic counter driver based on Timer Counter (TC) module for Atmel
SAM family.

Remarks:
- The driver is not thread safe.
- The driver does not implement guard periods.
- The driver does not guarantee that short relative alarm will trigger
  the interrupt immediately and not after the full cycle / counter
  overflow.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2021-07-26 05:13:40 -04:00
Mahesh Mahadevan 5c818f7f55 drivers: counter: Add counter for rt600
Add a RTC based counter for MXRT600

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-16 18:56:15 -04:00
Glauber Maroto Ferreira c344d0d74d esp32: drivers: counter: add support for general-purpose counters
Adds support for ESP32 general-purpose Counters

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-03-03 13:02:02 +01:00
Henrik Brix Andersen d31a1dc91b drivers: counter: add driver for the Xilinx AXI Timer
Add counter driver for the Xilinx AXI Timer v2.0 IP.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-11-17 19:30:20 -05:00
Hake Huang f6677b77fa counter: add pit counter driver
add Kinetis PIT as counter driver

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Filip Zajdel 33eabf6fc7 drivers: counter: Add native_posix counter hardware model and driver
Adds native_posix hw counter model and the counter driver.
Functionality is needed by software which is tested
on native_posix and has dependency on counter.
Hardware model was developed similarly to HW timer model.
The counter driver wraps HW counter functions and exposes
basic functionalities: starting, stopping, setting and cancelling
single channel alarms.
Code was tested against: tests/drivers/counter/counter_basic_api.

Signed-off-by: Filip Zajdel <filip.zajdel@nordicsemi.no>
2020-07-27 13:25:50 +02:00
Peter A. Bigot e444274e95 drivers: counter: add Maxim DS3231 support
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.

The basic functionality is exposed as a counter that is always running
at 1 Hz.  Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock.  This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2020-05-07 19:45:06 +02:00
Henrik Brix Andersen 85c996b016 drivers: counter: add NXP Kinetis LPTMR driver
Add counter driver for the NXP Kinetis Low Power Timer (LPTMR). The
driver can be configured either as 16 bit counter or 16 bit pulse
counter.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-03-27 11:17:58 -05:00
Ulf Magnusson bd6e04411e kconfig: Clean up header comments and make them consistent
Use this short header style in all Kconfig files:

    # <description>

    # <copyright>
    # <license>

    ...

Also change all <description>s from

    # Kconfig[.extension] - Foo-related options

to just

    # Foo-related options

It's clear enough that it's about Kconfig.

The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)

    git ls-files '*Kconfig*' | \
        xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-04 17:31:27 -05:00
Anas Nashif 27ff3f15f6 drivers: counter: remove qmsi counter driver
No users of this driver after dropping quark platforms.

COUNTER_0_NAME was only defined by the QMSI driver and was defined but
not used in DTS fixup files of ateml_sam0 SoCs. Removing those leftover
defines as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-09-18 11:06:18 -05:00
Tomasz Bursztyka 41c93a589c driver/counter: Add support for Microchip's XEC basic timer devices
Such basic timer is found on MEC150x for instance.
Since instances have dedicated data, let's define specifice instance
based on unique DT base address definition.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-09-14 12:13:49 +08:00
Loic Poulain 41bfeb54c2 drivers: counter: Add NXP MCUX GPT counter driver
Add driver for General Purpose Timer module which can act as a counter.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 11:53:07 -05:00
Charles E. Youse 783a43e265 drivers/counter/counter_cmos.c: implement counter with PC AT "CMOS" RTC
Enable use of the PC/AT "CMOS" RTC as a simple 1Hz counter.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-19 15:23:47 -07:00
Piotr Mienkowski d41f01d4c7 drivers: Define COUNTER_LOG_LEVEL using template
This commit updates counter Kconfig to use logger template to define
COUNTER_LOG_LEVEL option.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-06-17 16:38:46 -04:00
Piotr Mienkowski abbd952d2b drivers: Add counter driver (RTCC) for SiLabs Gecko SoCs
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.

Tested with SLWSTK6061A / BRD4250B wireless starter kit.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-06-10 22:27:25 -04:00
Derek Hageman a4f3e628e5 drivers: counter: Add SAM0 basic counter support
This adds support for the basic timer counter (TC) found on SAM0
series parts.  This driver only supports running the counter
in 32 bit wide mode.  Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.

Tested with tests/drivers/counter/counter_basic_api on SAMD21.

Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-05-28 09:23:44 -04:00
Erwan Gouriou 458226e1f7 drivers/counter: stm32: Provide STM32 RTC driver using counter API
Provides a STM32 RTC driver using new counter API.
Driver does not support wrap related functions (set, get, ..)

Fixes #11373

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-02-07 16:14:00 -05:00
Maureen Helm eb338915bb drivers: counter: Introduce mcux rtc shim
Adds a shim layer around the mcux rtc driver to adapt it to the zephyr
counter interface. Portions of this driver are reused from the existing
rtc driver in drivers/rtc/rtc_mcux.c.

The hardware supports a single alarm only and a fixed wrap value.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-02-07 16:14:00 -05:00
Stanislav Poboril f51ef0551c imx: Add IMX EPIT driver for i.MX socs
Add shim driver for i.MX EPIT (Enhanced Periodic Interrupt Timer)
peripheral which can be used for i.MX6SoloX, i.MX7D and other i.MX socs.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2019-02-07 16:14:00 -05:00
Krzysztof Chruściński 6b4ff1252a drivers: counter: Counter API implementation for nRF Series (TIMER).
Shim for counter API using nrfx_timer driver.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2019-02-07 16:14:00 -05:00
Ulf Magnusson 8308a51930 drivers: counter: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though, and is
inconsistent.

This will make the auto-generated Kconfig documentation have "No
defaults. Implicitly defaults to n." as well, which is clearer than
'default n if ...'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-07-03 17:11:31 -04:00
Vincenzo Frascino b1e02a594a counter: cmsdk: Add DualTimer as Counter
This patch adds Dualtimer to be used as a counter.

Jira: ZEP-1300
Change-Id: Ic4a2d89ec7fc0c0c2a0bc7f6d32d97637049faaf
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-23 15:15:54 -06:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Vincenzo Frascino fb7d483fbe counter: cmsdk: Add Timer 0 and 1 as Counters
This patch adds Timer 0 and 1 to be used as counters.

Jira: ZEP-1300
Change-Id: I9d8b971d8a3d76eee2f9cc4600e95729d67717a3
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-12-06 10:31:45 -06:00
Vincenzo Frascino f0fd6c2634 counter: Refactor main Kconfig file
This patch refactors the main Kconfig file in order to align it with the
Zephyr code style and to make sure that each Kconfig configuration
portion is easily identifiable.

Change-Id: Iba83be8ae154df4b29ff423b4c3cc97a78c93e00
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-11-30 14:39:10 +00:00
Kuo-Lang Tseng aebe38465f qmsi: aon counter: Use locking mechanism to guard critical regions of API call
This will guard critical regions in the driver API so that the API
operation called from one thread (task or fiber) can complete
without the context being over-written by any simultaneous call
of the API from other thread (task or fiber).

The locking mechanism is by default disabled in the build. To enable it,
the following flag needs to be defined:

CONFIG_AON_API_REENTRANCY

Jira: ZEP-424
Change-Id: I1b0eae70a4ab97229931033153662874d7c4a68e
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-07-21 02:05:43 +00:00
Kumar Gala 9ec2f3be80 Cleanup whitespace in Kconfig files
Convert leading whitespace into tabs in Kconfig files.  Also replaced
double spaces between config and <prompt>.

Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 13:28:07 -05:00