1. Update EDMA driver for version 4
2. The DMAMux module is not always present. Use the
feature define to make this optional.
3. Use the EDMA_SetChannelMux API for SoC's that supports
this feature.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit introduces a driver for NXP's eDMA IP.
The main reasons for introducing a new driver are the following:
1) The HAL EDMA wrappers don't support well different
eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
revision had to be introduced, thus requiring a new Zephyr
driver.
2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
don't use the DMAMUX IP (instead, channel MUX-ing is performed
through an eDMA register in the case of i.MX93).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add an emulated DMA driver. Emulation drivers are great to have
for each driver API for multiple reasons:
- providing an ideal / model driver for reference
- potential for configurable backend support
- seamless integration with device tree
- multi-instance, etc, for all supported boards
- fast regression testing of app and library code
Since many other drivers and lbraries depend on DMA, this might
help us to increase test coverage.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This commit introduces the SOF host DMA driver.
This driver is used by NXP platforms in the context of
SOF's host component to copy data from the host memory
to the firmware (local) memory. This is possible because
NXP platforms can access the host memory directly w/o
an actual DMA engine.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add new dt binding for edma v3 that inherits whole dt
properties from current version. One more property is
added for SoCs that don't have separate error interrupt
id, use same id with channel interrupt
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Introduce SMARTDMA dma driver. The SMARTDMA is a peripheral present on
some NXP SOCs, which implements a programmable DMA engine. The DMA
engine does not use channels, but rather provides a series of API
functions implemented by the firmware provided with MCUX SDK.
These API functions can be selected by the dma_config slot parameter. A
custom API is also provided to allow the user to install an alternate
firmware into the SMARTDMA.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Move most of the designware driver into a common compile unit with a
a header that exposes the common functionality.
This allows for derivative hardware, such as that in intel's adsp (cavs)
to use the common functionality while extending.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This patch prepares the dma and introduces the dmamux on soc series
which supports this feature for memory/periph transfers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There is no such thing as CAVS DMA IP block, the DMA IP block found on
CAVS based chips is made with DesignWare one.
This will help to centralize DW based DMA device into one driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the driver files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.
In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Add dma driver for Nios-II Modular Scatter-Gather DMA soft IP.
This driver relies upon the Altera HAL msgdma driver for all
the dma core register programming and interrupt handling.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.
This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.
Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As per current policy of requiring supervisor mode to register
callbacks, dma_config() is omitted.
A note added about checking the channel ID for start/stop, current
implementations already do this but best make it explicitly
documented.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
