Set the correct VCO input range for the PLL frequency
with each bit PLL1RGE of the PLL1CFGR register
This get_vco_input_range is similar to the stm32h7 one.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock divider value is not being applied as the address of the
register to which it is being written is incorrect. A check of all RA MCU
datasheets confirms that, in all cases, the SCKDIVCR register is at an
offset of 0x20 (and not 0x21).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Add definition for DMIC clock source to LPC SYSCON clock control driver.
This constant allows drivers to get the DMIC bit clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Some STM32F4xx chips have an R division factor in PLL. Add possibility
to configure that.
Even though the output from the R division is not used, it can be
increased to reduce power consumption.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Reduce code-complexity of stm32_clock_control_init() function, which is
used and exists for both M4/M7 cores.
Replace dublicated code by proper preprocessor guarding.
This change shall reduce code-errors and copy-paste errors since same
functional code is present only once now.
Identify even more common code
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
We should set the z_clock_hw_cycles_per_sec as the value of
the system clock frequency.
There was a mistake in referencing the clock source set before
initialization.
I corrected it to reflect the clock value after initialization.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add support for enabling the clock security system, which can detect
failures of the HSE clock.
Includes tests for nucleo_h743zi and nucleo_g474re.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
If RC32K oscillator was on during startup, calibration
work was never going to actually calibrate this oscillator.
It happen because lpc_clock_state.rc32k_started was only set when
oscillator was turned on after if was turned off.
Now lpc_clock_state.rc32k_started is also set when rc32k is already
started (possible during boot).
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Need to do the ENET module-level clock initialization from zephyr
instead of MCUX HAL, because now there are multiple zephyr drivers with
different init priorities that rely on the module being clocked. MDIO
must be initialized before the ENET MAC, and the MAC driver currently
calls ENET_Init from the HAL to initialize the clock, but MDIO needs the
module clock enabled first on some platforms. So replace the MAC init
with ENET_Up from the HAL, which doesn't include clock init, then do
clock init from a higher priority sys init based on the parent
compatible.
Also, add support for enet clock ungating with clock_control_on on ccm
driver do this with current platforms supported.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Due to a typo it is not possible to select the main oscillator (MOSC) as a
clock source for an RA Microcontroller. This patch resolves the issue.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Do not enable subsystem/driver shell modules by default and stop abusing
CONFIG_SHELL_MINIMAL, which is internal to the shell subsystem, to decide
when to enable a driver shell.
The list of shell modules has grown considerably through the
years. Enabling CONFIG_SHELL for doing e.g. an interactive debug session
leads to a large number of shell modules also being enabled unless
explicitly disabled, which again leads to non-negligible increases in
RAM/ROM usage.
This commit attempts to establish a policy of subsystem/driver shell
modules being disabled by default, requiring the user/application to
explicitly enable only those needed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds a clock control device for a PWM node, allowing the PWM
to be controlled using the clock control API.
It is a similar idea to the device driver in linux:
linux/Documentation/devicetree/bindings/clock/pwm-clock.yaml
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Define max SYSCLK and AHB clock frequencies as 280 MHz, max APB
frequency as 140 MHz, and enable semaphore clock.
Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
This reverts commit d963900dbd.
Since i.MX 93 is supported by mcux_ccm_rev2, remove i.MX 93 support
from mcux_ccm driver.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
i.MX93 share similiar register layout with i.MX RT11xx. Change ccm driver
to align with i.MX RT11xx, and make it easier to enable other drivers.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Unify spelling of CAN Flexible Data-rate abbreviation to "CAN FD" instead
of "CAN-FD". The former aligns with the CAN in Automation (CiA)
recommendation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Flash is clocked with HCLK, while CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
reflects SYSCLK. HCLK = SYCLK / AHB prescaler.
When dealing with flash latency, use HCLK instead of SYSCLK.
This changes reverts a abusive change done in an old commit (efd8ee465c)
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Latency should be set before HCLK clock increase. Not doing so can result
in broken behavior.
For instance, at startup, MSI is @4MHz on L4 series.
If MSI is required to be configured at 48 MHz for future use a USB clock,
this will be done in set_up_fixed_clock_sources(). If flash latency is
not correctly set at this point fetching flash will fail..
Move flash latency configuration before setting up fixed clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Based on RM0456, each PLL in the STM32U5 has the
capability to work either in integer or fractional mode.
In this update, the fractional mode can be enabled
by setting the fracn value in the device tree.
Signed-off-by: Jatty Andriean <jandriea@outlook.com>
Add an explicit include of zephyr/arch/cpu.h before fsl_clock.h so that
the Zephyr cpu definitions are parsed before the hal ones.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
According to the reference manual the overdrive should be enabled after
setup of the sysclock (HSE or HSI) and enabling the PLL (PLLON).
The flash latency should be enabled after the PLL has been turned on,
but before switching the system clock to the PLL.
Signed-off-by: Max van Kessel <max_van_kessel@msn.com>
LSI clock configuration for STM32WBA is located in backup domain.
The backup domain needs to be enabled before the LSI can be enabled.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
RCX and RC32K oscillators are not precisely trimmed.
This code allows to measure actual frequency of those two
oscillators.
Device tree binding were extended to specify calibration
interval. This interval (in seconds) is used to periodically
call work that will perform oscillator frequency measurement.
For XTAL32K settle time can be provided in device tree.
After this time (depending on actual oscillator used)
XTAL32K is assumed to be stable and low power clock driven by
XTAL32K is considered OK for precise usage in bluetooth.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
