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zephyr/soc
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Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig 
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-05 14:28:42 +02:00
..
arc ARC: boards: allow MWDT toolchain for nsim_hs6x and nsim_hs6x_smp 2022-05-10 14:12:25 -04:00
arm soc: pm: Microchip MEC172x SoC based power management 2022-06-05 14:28:25 +02:00
arm64 boards: imx8mm: add partial pin control support 2022-05-12 16:57:17 -05:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
riscv riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
xtensa boards: xtensa: Activate the intel_adsp west runner 2022-06-05 14:13:57 +02:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00