2236eaf52c
DDR50/DDR52 modes should use PINCTRL_STATE_SLOW (50MHz), so the lack of a break statement after enabling DDR mode is expected. Add an explicit __fallthrough to resolve the issue flagged by coverity scan Fixes #65324 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
||
---|---|---|
.. | ||
CMakeLists.txt | ||
ifx_cat1_sdio.c | ||
imx_usdhc.c | ||
intel_emmc_host.c | ||
intel_emmc_host.h | ||
Kconfig | ||
Kconfig.ifx_cat1 | ||
Kconfig.imx | ||
Kconfig.intel | ||
Kconfig.mcux_sdif | ||
Kconfig.sam_hsmci | ||
Kconfig.spi | ||
mcux_sdif.c | ||
sam_hsmci.c | ||
sdhc_spi.c |