zephyr/arch/riscv
Anas Nashif e25f31ab78 arch: guard more code with CONFIG_EXCEPTION_DEBUG
It should be possible to disable exception debug, which is enabled by
default to reduce image size. Add missing guards now that the option is
cross architecture.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-14 09:32:27 +01:00
..
core arch: guard more code with CONFIG_EXCEPTION_DEBUG 2023-12-14 09:32:27 +01:00
include arch: riscv: add ARCH_HAS_SINGLE_THREAD_SUPPORT 2023-05-12 09:56:40 +02:00
CMakeLists.txt riscv: syscalls: use zephyr_syscall_header 2023-06-17 07:57:45 -04:00
Kconfig arch: riscv: Trap handler alignment configuration 2023-09-05 16:16:46 +02:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00