zephyr/dts/xtensa/intel
Tomasz Leman ff2dd7f25a dts: xtensa: intel: Reorder ACE 1.5 power domain nodes
This patch reorders the power domain node definitions in the ACE 1.5
Meteorlake DTS file to improve readability and facilitate comparison with
the documentation.

Changes include:
- Reordering power domain nodes by their bit positions.
- No changes to the bit positions themselves; they remain as originally
  defined.

This reordering does not affect the functionality but makes the DTS file
more maintainable and easier to cross-reference with the hardware
specification.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-03-19 14:54:29 +01:00
..
intel_adsp_ace15_mtpm.dtsi dts: xtensa: intel: Reorder ACE 1.5 power domain nodes 2024-03-19 14:54:29 +01:00
intel_adsp_ace20_lnl.dtsi dts: adsp: ace20: remove lp clock 2023-09-18 10:35:23 +01:00
intel_adsp_cavs.dtsi dts: xtensa: intel: add HDA DMA interrupt defs for cAVS platforms 2023-08-31 09:59:10 -04:00
intel_adsp_cavs15.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs18.dtsi soc/xtensa/intel_adsp: fix interrupts typo 2023-12-20 09:16:45 -05:00
intel_adsp_cavs20.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs20_jsl.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs25.dtsi soc: intel_adsp: cavs: fix dts memory address format 2023-11-06 15:40:20 -06:00
intel_adsp_cavs25_tgph.dtsi soc: intel_adsp: cavs: fix dts memory address format 2023-11-06 15:40:20 -06:00