zephyr/dts/bindings/cpu/ite,riscv-ite.yaml

# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
# SPDX-License-Identifier: Apache-2.0

description: ITE IT8XXX2 RISC-V CPU

compatible: "ite,riscv-ite"

include: riscv,cpus.yaml
dts: it8xxx2 device tree and binding This commit is about it8xxx2 platform device tree. Add driver's binding files, and one device tree as sample. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw> 2020-09-09 05:26:54 +02:00			`# Copyright (c) 2020 ITE Corporation. All Rights Reserved.`
			`# SPDX-License-Identifier: Apache-2.0`

			`description: ITE IT8XXX2 RISC-V CPU`

ITE: dts: cpu/yaml: fix the name of compatible This name should be the same as cpus node in dtsi. After the power policy is added, the cpu-power-states in the CPU properties can be used. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> 2021-10-04 04:16:19 +02:00			`compatible: "ite,riscv-ite"`
dts: it8xxx2 device tree and binding This commit is about it8xxx2 platform device tree. Add driver's binding files, and one device tree as sample. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw> 2020-09-09 05:26:54 +02:00
dts/riscv: add missing `riscv,isa` fields and modify existing ones This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> 2023-09-05 15:15:25 +02:00			`include: riscv,cpus.yaml`