Switch the default MCUBoot FW Update mode from Swap & Scratch
to more preferable Swap & Move for the rest of NXP boards.
Delete the scratch partition. Save RAM & ROM.
Slot 0 has one additional sector, for use with
the swap move algorithm.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The MEMC driver in memc_mcux_flexspi.c is initialized
before the FlexSPI driver (flash_mcux_flexspi_nor.c)
and hangs during FlexSPI init. Initialize the FlexSPI
clock to 50MHz before the speed is set to the optimum
speed by the FlexSPI driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Updated the frdm_mcxn947 with support for the
CTimer counter.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Fixes warnings when building documentation due to additional SoC
names being part of the Kconfig symbols which they should not be
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This patch is to fix issue #71473.
The commit 0be0d2175b revert some change
introduced by hwmv2 which allows defconfig can be overlay, so revert
back defconfig to be full configure files which includes all items used
by the board variants.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The MAC address macros are ridiculous in this driver.
Rewrite to be simpler and use eth.h common function.
Also, clarify the mac address generation on the DT overlays.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for USBOTG on RW612 BGA board. This support was tested with
the USB console sample, as well as the USB DFU sample.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Board name contains the `adsp` suffix and so should the
defconfig. Otherwise, the build system won't be able to
fetch the board configurations.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
CSS was deprecated from the mcu-sdk. Removing driver from lpc55s36
to clear build error.
This is a temporary patch to remove the build error.
Fixes#69961
Signed-off-by: David Leach <david.leach@nxp.com>
Adjustments of dts and defconfig files to adjust for the MERGE removal.
The revert of MERGE requires specific dts and defconfig files for boards
which relied on the MERGE feature.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Splits configuration up that was merged as part of hwmv2 due to
the merged configuration feature being reverted
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Enable support for LCDIC on rd_rw612_bga. This support also enables
acceleration features such as DMA for LVGL, to improve performance
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pinctrl and board enablement for LPUART2, which is broken out to
P4_2 and P4_3 on the FRDM board.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Automatically select CONFIG_GPIO when the GPIO-controlled CAN transceiver
driver is enabled. Update board configurations to benefit from this.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
In preparation for adding AMP support for i.MX RT6xx family we need
to rename existing cm33 support files to more specific names.
e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts
This will allow us to later add support for Cadence DSP found on i.MX
RT6xx series.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
imxrt6xx are dual core devices featuring an ARM Cortex-M33
core and an Cadence Xtensa HIFI4 Audio DSP.
Currently only m33 core is supported. In order to support
the Cadence DSP we need first to do some code-reorganization
for m33.
We start by moving all cm33 related code to its own directory
and introduce the cpuclusters property in soc.yml file.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Fixs USDHC by setting PWR and CD gpio's correctly.
Adds missing button from the GPS module.
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Add pinctrl for SAI1 node. This means:
1) Adding definitions for the pads used by SAI1.
2) Creating a pin group and referencing it in
the SAI1 node via the `pinctrl-0` property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add pinctrl for SAI1 node. This means:
1) Adding definitions for the pads used by SAI1.
2) Creating a pin group and referencing it in the
SAI1 node via the `pinctrl-0` property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Enable clock control for i.MX8ULP. This consists of:
1) Adding a PCC node in the DTS
2) Adding a header file containing the definitions
of the clocks used by the peripherals to be enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Change, for audio DSP and M7 cores, SOC_<name> to match
the exact soc name.
Update the board files accordingly.
These configs are used in SOF and NXP_HAL, so change
sha for these modules.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
In future versions of Linkserver, specifying the core argument within
the device string will not be supported. Therefore, move the FRDM
MCXN947 board to specify the core directly instead of using the device
string.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- fix schematic link pointing to different board
- fix link to the board_defconfig file
- remove the "Debug Firmware" link that was not referenced anywhere
- add a link to the board user manual
- minor additions to the debug with J-Link section
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Enable DMIC on RW612 BGA board. The DMIC is enabled for both onboard
MEMS microphones for this board, and the board is enabled with the DMIC
sample and test
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add devicetree node for the accompanying, ssd1306-based display board
connected to connector P4.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Correct a few issues with the documentation that were causing rendering
issues, as well as the following changes:
- added blurb to debug section clarifying that the default debugger
firmware supports LinkServer
- updated serial terminal output with board name given when building
with HWMv2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
By default, LinkServer's memory map for the MCXN947 does not define
memory regions for the SRAM or peripheral bus in secure mode. This
results in gdb failing to read from these memory regions unless
explicitly told ignore the debugger memory map via
"set mem inaccessible-by-default off".
To resolve this, define memory regions for SRAM and peripherals in
secure mode via the commandline arguments passed to LinkServer in
board.cmake.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
