Added the new intel_adsp_hda_dma_get_attribute function that
returns dma controller attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Gives the stm32u5 dma driver a suspend function to
enhance the dma API.
This is a particular feature of the stm32U5 GPDMA
to suspend a channel.
A delay is required ;1ms is compatible with both stm32u5 platforms.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For the stm32U5 serie, the busy flag is handled as other serie.
When the DMA is overriden by other HAL drivers, the busy flag
is not considered.
Refer to https://github.com/zephyrproject-rtos/zephyr/pull/47645
There is no Mux for this GPDMA and fixed 16 channels.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There is no DSPRA registers (0x71a60) in SOC Intel ACE.
Therefore this space should be not accessed. It is valid only
for some Intel CAVS SOC versions.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
GPDMA should work with disabled interrupts in ctrl_lo
This also helps with stability in SOF scenarios
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
For larger transfers DMA can be used enabling other tasks
to continue running. A threshold of 32 byte transfers
is about right and is defined threshold value for using DMA.
This does not currently support multiple SPI transactions changing
chip select with DMA (though the hardware supports this) currently.
Instead opting for the simpler first change of enabling one shot
DMA SPI transfers for those where the size warrants it.
Adds the loopback binding option to enable the spi_loopback test.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add the support of the stm32MP1 family for DMA peripheral.
This dma driver is similar to the stm32H7.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
If cfg_hi and cfg_lo are not set to zero in config setting, different
dma slot value is bitwise ORred to the previous set value. Thus fix it.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
For Intel ACE1.x the GPDMA link list structure should be aligned
to 64 bytes to avoid the link list entry fetch crossing the 64 bytes
address alignment.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix the scope of some variables in various STM32 drivers including:
- SDMMC
- DMA
- OSPI/QSPI Flash
- Interrupt controller
The variables are set static instead of global and const if appropriate.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This will use DW_CFGH_DST instead of DW_CFGH_DST_PER
to correctly setup cfg_hi. This is critical for ALH transfer.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This will trigger link commit immediately after start
to fix hda start flow.
Applies to link out only.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
For HDA link suspend is exactly the same as stop
but the same api is used also to control gpdma with unique suspend
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Update DMA drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit is converting the DMA kconfig for the stm32 dma driver
with new macro DT_HAS_<COMPAT>_ENABLED.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is frequent to find variable definitions like this:
```c
static const struct device *dev = DEVICE_DT_GET(...)
```
That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
DMA controller ownership can be done in the driver
initialization, it does not need to be part of the SoC. It simplify
the code and remove duplicated definitions.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
The commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
This commit controls the stream busy flag of the dma channnel
Set as true : stream is busy each time the channel is
started or reloaded.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When the channel is overriden by the HAL,
the dma irq must always be handled (even if not busy).
Only when the dma channel is not overriden by the HAL
the irq is exiting when the channel is no more busy.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Fixes configured DMA direction for HDA link in/out drivers.
Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
when the dma channel is stopped, the irq is no more
relevant ; clear any irq but do not process it.
Fix Typo on comments and add LOG_DBG on channel increment.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds a log backend that maintains a ringbuffer in coordination
with cAVS HDA.
The DMA channel is expected to be given some time after the logger
starts so a seperate step to initialize the dma channel is required.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Includes the definition of the STM32_DMA_STREAM_OFFSET
depending on the peripheral to adjust the first DMA channel
in the list of streams.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This change is controlling of function parameters before
configuring the STM32_DMA_HAL_OVERRIDE mode.
Then, in case the DMA channel is not valid (wrong ID) or busy,
an error occurs before overriding the DMA channel.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
SOCs using the EDMA IP that supported caching must locate EDMA transfer
control descriptors (TCDs) in non cacheable memory. For M7 cores, this
can simply use the "nocache" section. For M4 cores, where the nocache
section does not exist, the chosen SRAM section must be a tightly
coupled memory block which cannot be cached. Add a note to all boards
with M4 SOCs that support caching explaining this issue, and enable EDMA
driver to locate TCDs in SRAM.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This PR fixes up the Scatter-Gather EDMA mode for the MCUX EDMA Driver,
as well as enabling the dma reload feature for the same EDMA Driver.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Multiple instances of the device would have inadvertently shared the
LLI pool potentially causing nasty bugs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Rather than defining them in the header, require a set of defines
be provided to cavs_hda.h as part of the expected input to the API.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Ports the SOF DesignWare DMA code to Zephyr.
Effectively replaces much of what was the designware driver as this
driver enables scatter gather which the older driver did not.
* Enables cyclic transfer description lists when the cyclic config
param is given.
* Enables linear link position usage with cAVS GPDMA.
* Passes suspend/resume, scatter/gather tests.
* Provides status updates of the transfer through dma_get_status()
* Enables reloading a cyclic transfer with dma_reload()
* Enables dma handshakes using the dma_slot config param.
* cAVS specifics remain in the dma_cavs_gpdma driver.
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Co-authored-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Re-running the script that checks for the const qualifier missing on
struct device ISR's parameter.
The script also changes the parameter 'arg' to 'dev' when relevant.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Moves the nios2 msgdma driver device config struct to the device data
struct for mutable data. The config struct is expected to be const.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix a couple of issues reported by checkpatch:
ERROR:POINTER_LOCATION: "(foo*)" should be "(foo *)"
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It turns out XCC didn't like this change as it doesn't have a
__COUNTER__ builtin. Bummer.
This reverts commit e8389f2f53.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The PCIe device can be obtained at compile time, so make code more
efficient thanks to that.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Makes the IRQ_CONNECT macro statically declarable for Xtensa (nothing
prevented it except its structuring). Allows for IRQ_CONNECT usage
on a xtensa only platform to be declared statically avoiding the
fluff of setting up and enabling irqs for cavs gpdma.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Move most of the designware driver into a common compile unit with a
a header that exposes the common functionality.
This allows for derivative hardware, such as that in intel's adsp (cavs)
to use the common functionality while extending.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Device 'data' variable name was incorrect due to recent treewide naming
cleanups. Fix variable name to fix build error.
Fixes#42118
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Let's have dev_data for dev->data so it will not conflict with struct
call_back data variable.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Coverity identified valid error where the routine does a NULL
check for two different pointers after they have been dereferenced.
fixes#39868fixes#39874
Signed-off-by: David Leach <david.leach@nxp.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init struct for DMA peripheral is allocated in stack
and must be initialized (e.g. with LL_DMA_StructInit here)
to avoid loading undefined values in the DMA peripheral
registers.
Signed-off-by: Abel Radenac <a.radenac@lacroix-sofrel.com>
Refactors all of the DMA drivers to use a shared driver class
initialization priority configuration, CONFIG_DMA_INIT_PRIORITY, to
allow configuring DMA drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Not all STM32 parts have at least 5 DMA interrupt vectors for DMA2. In
particular, some STM32F1 XL-density devices only have 4 DMA2 interrupt
vectors, with Channels 4 and 5 sharing the same vector. Added
#if DT_INST_IRQ_HAS_IDX(1, 4) to prevent compiler errors on these SoCs.
Signed-off-by: Josh Hansen <jhansen3141@gmail.com>
fixes peripheral drivers such as async uart that rely on dma being
ready failing because dma is not initialized yet.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
The code was wrongly calling DMA_Abort on a channel
that not initialized. This fixes Issue#38078
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
In the dma.h there is a dma_ctx structure using a magic code
to be identify. This structure must be prepared as a new
element of the dma_stm32_data.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the configuration of the stm32h723 where the
dma1 & dma2 of type V1 with a MUX. Even if DMA is of type V1,
the 'feature' does not exist with DMAMUX
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The flag source_periph seems to be incorrectly set in dma_stm32.
In case the transfer direction is from periph to mem, then the
stream->source_periph is 1 (true) else it is false.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the dma V2bis which is particular DMA V2 instance for
stm32F1 and STM32L1 soc series. This DMA does not use the dma slot
Otherwise it is similar to version V2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In stm32l5xx soc, the LL_DMA_InitTypeDef has 2 more fields
(DoubleBufferMode and TargetMemInDoubleBufferMode) that must be
initialised with 0 else the configuration is wrong and gives
wrong values to the LL_DMA_Init function. Due to this the test
tests/drivers/dma/loop_transfer too would fail.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
The STM32F0 MCUs (except STM32F030XC) don't have a DMA channel selection
register (DMA_CSELR). This patch fixes the build of the dma_stm32 driver
for them.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
The request id is given by the DMA request MUX id which start at offset
1 and are vaid until req_nb + gen_nb.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit continues simplifying the generation of
isActiveFlag/clearFlag funtion pointer array for the request generators
and does the same for the table_ll_channel.
Additionally move struct dmamux_stm32_channel to c file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit uses dt property dma-channels instead of ll defines to
make sure every soc has correct number of function pointers defined.
While commit 5f6218a tried to fix this for g0 series, this caused
regression for other series(e.g. stm32g431). Using UTIL_LISTIFY and
dt properties this should finally be fixed and reduce boilerplate code.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
1. Update the SDK API's called in the configure implementation.
The DMA_PrepareTransfer and DMA_SubmitTransfer SDK functions
are not recommneded for use. Replaced the call to these SDK
functions with other SDK API's.
2. Fix the implementation the configure function when multiple
blocks are used.
3. Update the dma_reload implementation. The old reload function
would simply abort the transfer. The new implementation reloads
the DMA buffers for transfer.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix stm32_dma_is_irq_active not checking the IRQ status(IsEnabled) for
active interrupts.
While the transfer-complete, half-transfer comp. and transfer-error
is_XX_irq_active() functions check for IRQ status (IsEnabled),
ORing the result with dma_stm32_is_gi_active() overrides the
status check as gi is always 1 in case any of these flags is active.
Related to commit 96c92ed93f.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use LL_DMAMUX_CHANNEL_x defines instead of DMAMUX_CSR_SOF7x to check
if corresponding LL_DMAMUX_IsActiveFlag_SOx and LL_DMAMUX_ClearFlag_SOx
inline functions exist and should be added to func_ll_is_active_so[]
and func_ll_clear_so[].
The HAL of some socs uses the same flag to decide which registers exist
on a specific soc. And the same defines are used for table_ll_channel[]
initializations.
This is necessary because DMAMUX_CSR_SOF5 and DMAMUX_CSR_SOF6 were
wrongly added in the HALs soc header file for some stm32g0 socs,
therefore without this change some stm32g0 socs couldn't compile.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the existing driver to support STM32G0 series.
It enables the DMA_STM32_SHARED_IRQS flag for g0 series, such that
all interrupts are handled in a shared isr to avoid irq conflicts.
The shared isr is extended to be able to handle irqs from more than one
dma instance.
Furthermore the config_irq function of instance 1, which connects to the
irqs, was reworked to avoid irq conflicts when 2 dma instances on
stm32f0, or stm32g0 are enabled:
While dma1 has one exclusive irq for channel 1, and one irq for dma1
channels 2 and 3, all other channels share the same irq.
Therefore it is currently not possible to enable dma2 without enabling
dma1 at the same time, without getting an build errror due to an irq
conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not all STM32 Series can enable a dedicated clock for dmamux.
In stm32g0 series for example the clock is enabled automatically
as long as either DMA1 or DMA2 is enabled.
This commit changes dmamux driver to cope with socs that don't have
defined a clocks property. Therefore it moves the config(and data)
struct into the c file to be able to use DT_INST_NODE_HAS_PROP macro.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the missing parts for adding support
to stm32h7 dma driver.
The fix is to make dmamux driver work with
dma v1 driver.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
1. remove redundant protection on channel status
2. update link interface to support major and minor link
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Enable half transfer interrupt of the dma controller
in case the channel was enabled in circular mode.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Increase BD buffers from 7 to 9 to handle 1024 block
counts having mega/normal src,dst bd combinations in one request.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Sync packet is always CARD to HOST and if it's combined with HOST
to CARD transfers in one single RM header packet, it's not allowed
due to RM implementation constraints. RM implementation allows same
type of data transfer direction in all the BD's populated under one
header BD.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Zero initialize the ch_handle in dma_pl330_configure().
The memset in dma_pl330_config_channel()is incorrect,
as the ch_handle is already populated with valid values and
the dma_pl330_config_channel() is overwriting with zeros.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
All dma drivers are devicetree based now so we can remove the last
bits of Kconfig associated with the old driver style.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Conver the NIOS-II mSGDMA driver to be devicetree based. Add node for
dma controller into nios2f.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When running the tests of the async api of uart
on nucleo-l4r5zi we get MPU fault.
The reason is ordering initialization. The uart and dma
drivers are initialized PRE_KERNEL_1 while dmamux is
initialized POST_KERNEL.
Thus, the function device_get_binding fails since the
dmamux device is not ready to be used.
Fixes: #32715.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Move dmamux_stm32_channels struct from device data to device
configuration and initialize the dmamux channel - dma channel
assignment during build time,
as this association is hardwired in all known series.
The information is taken from dma_offset and dma_requests device tree
properties. The current implementation is valid for series with either
a single or two dma peripherals and a single dmamux peripheral.
Both dmas can independently enabled.
As the driver uses multi-instance DT_INST_DEFINE, also macros for a
second dmamux are are added that should allow easier extension to a
second dmamux instance.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Drivers are using DEVICE_AND_API_INIT which is deprecated so convert
the iproc_pax dma drivers over to using DEVICE_DT_INST_DEFINE and
DEVICE_DT_INST_GET.
Fixes#32153
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When checking for IRQ flags, we should also check
for IRQ status (IsEnabled ?).
If this is not done we can end up in Half Transfer
interrupt processing while it is not enabled.
Additionaly always use the id translation function
in LL API calls.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add `get_status` function to dmamux driver api.
This uses the regular dma driver `get_status` function.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Convert driver(s) to DEVICE_DEFINE instead of DEVICE_AND_API_INIT
so we can deprecate DEVICE_AND_API_INIT in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It raises an error in case the source data width differs
from the dest data width.
The dma_stm32_width_config function is no more useful: removed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This new offset value in the dma config is made to
build the table of dma mux_channels with a dmamux.
Range depends on the nb of channels for selected dma instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1, Change the allocation of DMA descriptors for the case
when multiple buffers are used for DMA transfer. This was
tested during SPI DMA transfers
2. Add support for the case when source and destination
addresses should not be incremented.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Not possible to use device_get_binding() because we are
currently initializing DMA_1 device, so it is not ready and
device_get_binding() will fail.
Directly use string compare is more efficient.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32_dma_disable_stream first checked if the stream was
disabled and if so returned OK. If it wasn't disabled it
tried to disable it and returned -EAGAIN.
The function is used in loops that try to disable the stream
by calling this function and if it fails wait for 1ms and
retry.
Becuase this function the first time (if the stream wasn't
disabled already) fails there is always a 1 ms delay. For
the SPI driver, that has a RX and TX stream, this means
a 2ms delay between the last data and CS going high.
By first trying to disable the stream and than checking
if it succeded most of the time the first call disables
the stream and the 1ms delay isn't needed.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use dma_stm32_disable_stream instead of stm32_dma_disable_stream
to check if the disabling of the stream really worked and if
not return an error.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Convert global conversion tables for id-to-stream and slot-to-channel
to functions that use local const static conversion tables.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
- Remove the need for kmalloc
- On hardware that supports it use 1 IRQ handler per stream to
determine the stream ID, so the ISR does not have to loop
over all ID's to see which one is active. On hardware (like
STM32L0 and STM32F0) where up to 7 streams share 3 IRQ's use
the loop to check which stream is active.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use volatile for flag shared between normal code and ISR to
prevent the compiler from possibly optimizing it away.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
These are all the case that coccinelle cannot find as they are inside
macro declarations.
Fixed via:
git grep -rlz -E "\(struct device \*" |
xargs -0 sed -i 's/(struct device/(const struct device/g'
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Passing the device's config was necessary, and wrapping device inside
it.
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add support for the NXP KE1xF SoC to the eDMA driver. The KE1xF supports
m2m DMA transfers from sources 60 to 63.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
DMA driver shall be initialized before any of its
clients. Right now, its initialization priority is
lower than that of UARTs. So, increase its init
priority to support future async uart drivers.
Signed-off-by: Jun Li <jun.r.li@intel.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Replace individual device instance definitions with the macro that
expands to the equivalent change.
F='struct device DEVICE_NAME_GET'
git grep -l "$F" \
| xargs sed -i -r \
-e "s@$F"'\(([^)]*)\);@DEVICE_DECLARE(\1);@'
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.
There are a few exceptions:
- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
would require more time to convert than I have at the moment. For the
sake of expediency, just inline the DT_HAS_DRV_INST expansion for
now in these cases.
- SoC drivers which are explicitly single-instance (like the nRF SAADC
driver). Again for the sake of expediency, drop a BUILD_ASSERT in
those cases to make sure the assumption that all supported SoCs have
at most one available instance is valid, failing fast otherwise.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This reverts commit 90cc723e65.
Using `DMAC_CHCTRLA_TRIGACT_BLOCK` breaks SERCOM UART peripheral DMA
operations (DMA-based asynchronous UART transmit operation only sends
the first byte and does not proceed any further).
The `DMAC_CHCTRLA_TRIGACT_BURST` with `DMAC_CHCTRLA_BURSTLEN(0)` is a
special case utilising the "internal FIFO", according to the datasheet
(see DS60001507E; 22.6.2.8), and should always be specified for
peripheral data transfer operations.
Also it is worth noting that Atmel and other third-party drivers use
the aforementioned "internal FIFO" configuration for peripheral data
transfers as well.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The channel direction for a V1 DMA is not allowed to be memory to memory
and there is a check in place for this. However, the check is being
performed on the stream prior to actually configuring the stream. This
results in the check always failing regardless of the channel direction.
The check has been modified to be performed on the incoming
configuration.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
This patch prepares the dma and introduces the dmamux on soc series
which supports this feature for memory/periph transfers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch is disabling the dma channel before reloading
source and dest for memory and peripheral addresses
Then the channel is enabled to re-launch the transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
define the irq handler in case of DMA V1 or V2,
for the stm32x soc series
with DMA V1 raise Fifo Error if enabled
with V2, handle the Global Interrupt
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Return an error if the direction of the channel is wrong
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move tables declaration as they are only used locally for now
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Control values when configuring the dma channel
According to the soc specification,
the dma V2 channel counts from 1.
the dma V1 stream counts from 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When a DMA stream is successfully disabled, the function should
immediately return with a success status.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
Fix the definition of DMA_SAM0_IRQ_CONNECT
pre-processor directive, so that it calls
DT_INST_IRQ_BY_IDX macro instead of
DT_INST_IRQ_HAS_IDX macro.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
