This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.
As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
