add dts support for watchdog to accomodate watchdog driver bringup on
aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
i.MX93 share similiar register layout with i.MX RT11xx. Change ccm driver
to align with i.MX RT11xx, and make it easier to enable other drivers.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
The labels used in chosen node are not defined in dtsi file.
They are defined on board level and also chosen is already set there to
proper values.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
No reason to declare it per node, as it is almostly shared by all
peripherals.
Also introduced `DT_FREQ_M` macro for better readability.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Some Ethernet PHYs used the devicetree node name `phy`, while others
used `ethernet-phy`. Be consistent and use `ethernet-phy` throughout.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
The interrupt-map was missing the priority field.
This causes a build failure when trying to use it.
The lines are split to fit into the 100 column limit.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Now that all in-tree phys are declared under their mdio bus, drop the
`mdio` property and use DT_INST_BUS to find the bus.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Rework the devicetree definition for smsc91x to put the mdio and
ethernet device at the same level, and make the phy a child of the mdio
node.
This allows matching up the device initialization sequence with the
devicetree hierarchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
adds dts support for general purpose timer to accomodate timer driver
bringup on aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Some register addresses change within the AM6X family.
AM62X is common to AM623X/AM625X processors.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.
- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Enable all cpu cores in soc dts and disable unused core in board dts.
2. Use default irq priority for uart interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
