Fix handling of gpio-reserved-ranges within MCUX iGPIO driver, to ensure
that the configuration IDX will be correctly calculated for pins where
multiple reserved ranges are present on the GPIO controller
Fixes#52506
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
If the bootloader changes iof_en/iof_sel settings before zephyr launching,
GPIO does not behave correctly.
These values should be 0 initially, Initialize to 0 at GPIO initialize.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Common GPIO driver needs to be initialized before e.g UART driver
to ensure correct GPIO clock configuration when configuring UART pinout
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.
Enable nocache in each driver use it.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Change Summary:
Update Base addr to set direction to use Aligned IP base address instead
of Port Base Address. Port Base Address + offset to direction register
will set incorrect value for Port B,C & D. For ex: In cases when more than
1 port is configured on the same IP, the DTS node for port B will start
at offset 0xC. Calculating the port using Port Base will yield offset of
PORTB DIR register which is at offset 0x10 from Aligned Base, and as a
result will result in setting DIR register of PORTC instead.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
Change Summary:
Moving the setting of Pin direction before setting/clearing the pin
configured as output for the change to correctly take place.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This commit adds support for get_config and get_direction functions
for the nct38xx IO expander family.
Also applies the clang-format changes.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This commit fixes the comment and adds the missing assignment of
return value from i2c read byte command in the nct38xx driver.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
In npcx ec series, two detection levels, 3.3V (default) and 1.8V are
supported during gpio configuration. But the current implementation
always selects default detection level whether NPCX_GPIO_VOLTAGE_1P8 is
set. This PR is a fix for this issue.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
RT1718S is an i2c-based TCPC chip that supports 3 additional GPIOs.
The pins can be used for USB-C operations e.g. handling FRS, but they
can also work as usual GPIOs.
Add a driver for the RT1718S GPIO and a handler for an alert signal from
the chip. The handler reads the alert register once asserted and calls
the GPIO interrupt handler if needed(Vendor-defined alert).
gpio_rt1718s.c file and "richtek,rt1718s" node collect common properties
and data for all RS1718S functionalities. The file can be extended for
TCPC driver. rt1718s.h file also defines inline functions with i2c
operations common for all drivers. The common header and source files
can be moved to tcpc directories once the tcpc driver is added since it
is the main functionality.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
`struct device::config` is a `const void *`, so this struct does not need
to be mutable.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Parts of the macro used `inst`, others `n` for the instance number; only
`n` was actually defined (so `inst` expanded to the empty string, causing
name errors with more than one instance).
Unify everything to `inst`.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The NPCX driver did use deprecated voltage macros. Define vendor
specific flags instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The pin get function was using deprecated macros. Note that the set
implementation already uses vendor specific flags.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fixed how data is read in mcp23sxx_read_port_regs
The data is now stored in an array to get the
actual data from spi
Signed-off-by: Daniel Skatt <daniel.skatt@gmail.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Zephyr implementation is limited to 4 IRQ per GPIO bank when up to 8 is
theoritically possible.
It is now possible to use until 8 IRQ per GPIO bank. This can be
achieved with minimal effort in a device tree overlay:
&gpio0 {
interrupts = <4 2>,<5 2>,<6 2>,<7 2>,<32 2>,<33 2>;
};
&gpio1 {
interrupts = <34 2>,<35 2>;
};
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
Fix the enabling of the independant IO supply.
Function LL_PWR_EnableVddIO2 is called LL_PWR_EnableVDDIO2 on U5.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adds open drain support to atmel,sam-gpio drivers, by writing to the
PIO_MDER or PIO_MDDR registers during gpio configure.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Implement GPIO driver minimal API's for NXP S32 devices, based on SIUL2
peripheral. SIUL2 allows to control the pins electrical characteristics
such as internal pull resistors, pin direction and more.
GPIO driver API's for interrupts will be implemented in a future patch.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Register definition header was missing, SoC common header as well (for
ite_intc_get_irq_num).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Previous commit removed pinmux from the platform but neglected to
remove the dependency in this Kconfig resulting in build failures
when target application configures GPIO support.
Fixes#51144
Signed-off-by: David Leach <david.leach@nxp.com>
Clean up and refactor x86 SoC headers in preparation of adding
new platforms in the future.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
