Commit graph

9 commits

Author SHA1 Message Date
Nicolas Pitre df6084fec1 riscv_machine_timer: remove unused config option
This should have been removed in commit 11a2107d99 ("riscv: timer:
driver revamp").

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-06-01 04:53:19 -04:00
Khor Swee Aun c93c853cba drivers: timer: Machine timer driver enablement for NIOSV
Update machine timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on NIOSV devicetree.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-02-20 09:29:13 -05:00
Shawn Nematbakhsh cd0f54fb88 drivers: timer: riscv_machine_timer: Add support for OpenTitan
OpenTitan uses a timer compliant with the RISC-V privileged
specification.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-27 19:25:26 +09:00
Kumar Gala e11074d2a7 drivers: timers: riscv: don't leak Kconfig symbols
Add if check around RISC-V machine specific kconfig symbols so they
aren't exposed to everyone.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-11-02 15:40:59 +09:00
Kumar Gala cc2c05a90c drivers: timer: Update drivers to use devicetree Kconfig symbol
Update timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Filip Kokosinski 70c978bb97 soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue

The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.

The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.

The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-05-24 08:58:43 -07:00
Nazar Kazakov 9713f0d47c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-14 20:22:24 -04:00
TOKITA Hiroshi d79d4f0bea riscv_machine_timer: Enable to use divided clock for the machine timer
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
Gerard Marull-Paretas 24a169e329 drivers: timer: split Kconfig
Split Kconfig into individual files for each driver. This improves
overall readability of the Kconfig options.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-12-04 07:34:53 -05:00