The commit restricts erase-value to either 0xff or 0x00.
On program-erase type devices writes can only change from
erase value of bit to opposite, ease usually consists of two
operations which is programming the opposite value to every bit
of erase range and then turning back all bits to the "erase-value";
above makes it impossible to have erase value of device to be other
than 0xff or 0x00.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
add gpio_intel driver with acpi based resource enumeration support.
Also updated test cases overlay with new dts entires.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
The ace20 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The ace15 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The tgph description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set RTC clock source to the internal 32 KHz LPO. Currently RTC clock is
used to source RTC counter and FTM counter.
Fixes#71289
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO. To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.
The original PIO source code is also included as a reference.
Corrected 3-wire tx/rx counts.
Enable half-duplex code based on DTS configuration
Replace runtime checks with static BUILD_ASSERT()
Remove too-fussy Kconfig options
Removed PIO source per review request
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The MAC address macros are ridiculous in this driver.
Rewrite to be simpler and use eth.h common function.
Also, clarify the mac address generation on the DT overlays.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds a DAC driver for Texas Instruments DACx0501 family of devices
Signed-off-by: Eran Gal <erang@google.com>
Co-authored-by: Martin Jäger <17674105+martinjaeger@users.noreply.github.com>
Add a VEVIF node to be used for communicating with SysCtrl (cpusys).
This is the only part of the SysCtrl VPR exposed to local domains.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Enable MIPI mode to be set via devicetree, for displays that support
multiple MIPI DBI modes. This commit also adds new helpers for displays
that allow drivers to initialize the entire MIPI DBI configuration
structure from devicetree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates the SRAM configuration in the STM32L475 device tree:
- `sram0` size reduced from 128K to 96K.
- `sram1` added with 32K.
These changes correct memory settings to prevent initialization failures.
Signed-off-by: Tianshuang Ke <qinyun575@gmail.com>
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
If I2C3 switches from GPH1/GPH2 to GPB2/GPB5, extend setting
is required.
Test: Accessing I2C is normal if I2C2, I2C3, I2C5 are switched.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Copy the DMA channel information to both UART and SPI
instances of the Flexcomm as only one of them can be
active.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all devices are initialized at boot time (following their
level and priority order). This patch introduces deferred
initialization: by setting the property `zephyr,deferred-init` on a
device on the devicetree, Zephyr will not initialized the device.
To initialize such devices, one has to call `device_init()`.
Deferred initialization is done by grouping all deferred devices on a
different ELF section. In this way, there's no need to consume more
memory to keep track of deferred devices. When `device_init()` is
called, Zephyr will scan the deferred devices section and call the
initialization function for the matching device. As this scanning is
done only during deferred device initialization, its cost should be
bearable.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
CSS was deprecated from the mcu-sdk. Removing driver from lpc55s36
to clear build error.
This is a temporary patch to remove the build error.
Fixes#69961
Signed-off-by: David Leach <david.leach@nxp.com>
Configure the 'soft-off' power state for manual selection only in the
DTS for Intel ADSP ACE 1.5 MTPM and ACE 2.0 LNL platforms.
Changes include:
- Setting 'min-residency-us' to 0 to indicate that the 'soft-off' state
is not intended for automatic selection by the power management
policy.
- Adding a 'status' property set to "disabled" to prevent the power
management policy from using this state during its decision process.
The 'soft-off' state remains available for manual selection by calling
`pm_state_force`. This change ensures that the state can still be used
when explicitly requested by the system or application, providing
flexibility for power management operations.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Implement a sensor for the output diagnostics of the power train
switch TLE9104.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
