Include the CANopenNode module integration files in the CAN bus
maintainers group and assign ownership to me.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
One limitation of the current IPM API is that it is assuming that the
hardware is only exporting one single channel through which the data can
be sent or signalling can happen.
If the hardware supports multiple channels, the IPM device must be
instantiated (possibly in the DT) several times, one for each channel to
be able to send data through multiple channels using the same hw
peripheral. Also in the current IPM API only one callback can be
registered, that means that only one driver is controlling all the
signalling happening on all the channels.
This patch is introducing a new MBOX API that is supporting
multi-channel signalling and data exachange leveraging and extending the
previous (and outdated) IPM API.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This is a driver for the Synopsys DesignWare MAC. It should work
with the "DesignWare Cores Ethernet Quality-of-Service" versions 4.x
and 5.x.
This driver uses a zero-copy strategy, meaning that the hardware
reads and writes data directly from/to packet fragment buffers
provided by the network subsystem without first copying the data into
a dedicated DMA bounce buffer.
Platform specific setup is necessary for the hardware to work.
Currently, only the STM32H7X series is implemented and tested.
While this part needs refinement, this driver performs better and uses
far less code space than the HAL-based alternative.
Not yet implemented:
- MDIO (it is WIP, currently relying on default PHY config)
- PTP support
- VLAN support
- various hardware offloads (when available)
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Take ownership of all the neorv32 specific files (dts bindings, soc
implementation, drivers, and board definition).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This is used by autoPTS project so make sure Szymon is aware of all
changes in tester application.
Signed-off-by: Szymon Janc <szymon.janc@codecoup.pl>
Import any manifest files in a new 'submanifests' directory into
west.yml.
This lets users define custom zephyr modules or easily override
built-in modules by dropping their own manifest files into
submanifests/some-user-file.yaml.
Provide an example and a README with links to the relevant
documentation in 'submanifests' to get users started.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add an application agnostic State Machine Framework library to
Zephyr that provides an easy way for developers to integrate
state machines into their application.
Twister passed:
twister -T tests/lib/smf/
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
1. Add support for multiple syscon entries (as a side effect, this also
fixed syscon.c implementations which weren't being linked to their
syscon.h counterparts).
2. Add support for different width registers in syscon.
3. Add tests for syscon
Signed-off-by: Yuval Peress <peress@chromium.org>
This adds driver for EOS_S3 SoC FPGA.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Add a shim that allows using the nrfx PDM driver via the Zephyr API.
Add also missing devicetree nodes representing the PDM peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-pdm" binding with a new property that allows
specifying the clock source to be used by the PDM peripheral (so that
it is possible to use HFXO for better accuracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This script allows us to programmatically query bug-bashers within
a user-supplied time-window.
For example, we held a "Bug Bash Week" August 1-7, 2021 (it was
announced a week early though). The output of the script prints
the "top ten" bug bashers in tab-separated columns in descending
order. The first column is the number of bugs squashed and the
second column is the github user id.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Add myself and Teng-Shih-Wei as owners for andes_v5 soc series, dts,
adp_xc7k_ae350 board, and device drivers from Andes.
Signed-off-by: Jim Shu <cwshu@andestech.com>
to make use of Espressif's hal in order to ease both
driver maintenance and code reuse between socs.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit adds support for Ethernet PHY drivers via a PHY API.
It also includes a driver for a generic MII compliant PHY
which supports most PHYs on the market.
Separating PHY driver from the SoC specific Ethernet driver
simplifies the Ethernet driver code and enables code re-use.
Drivers for specific PHYs with more advanced features, such as
RGMII delay in PHY can be developed independent of the Ethernet
MAC driver.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
This commit adds support for the Legend 2.5" boards (legend25_ssd and
legend25_hdd) based on the STM32F070CB MCU. These boards can be found in
the Seagate FireCuda Gaming Drive, Gaming Drive for Xbox, SSD Gaming
Drive for Xbox, and Gaming Drive for PlayStation devices. Both boards
contain the following hardware components:
- A B1414 LED strip connected to the PA7 pin (SPI MOSI)
- A SPI flash (FM25F005) connected on SPI2 bus
The Legend 2.5" HDD board also contains an activity LED connected on
TIM3 CH3
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
based on uart rom functions, also enable console driver
on top of this driver, which enables logging
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
We try to reduce the ambiguity between 'soc/nuvoton/' and
'soc/nuvoton_npcx' folders. Most if soc vendors name their soc folder by
the company name with SOC_FAMILY suffix instead of the company name
directly. It is clearer if the soc company has different product lines
that aim to specific markets.
In this CL, the 'numicro' suffix is used for Nuvoton Microcontroller
production line. It distinguishes the 'npcx' suffix that used for
Nuvoton Embedded Controller (EC) of Notebook PC product line.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The driver only support use case where the channels are used in mutual
exclusion.
Origin: Original
Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Add a shim that allows using the nrfx I2S driver via the Zephyr API.
Add also missing devicetree nodes representing the I2S peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-i2s" binding with a new property that allows
specifying the clock source to be used by the I2S peripheral (so that
it is possible to use HFXO for better accurracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
All the macro for dma-cells are now in the
include/drivers/dma/dma_stm32.h header file.
So the include/dt-bindings/dma/stm32_dma.h is no more
useful and removed from #include.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move @MulinChao, @WealianLiao, and myself from code owners entry
dts/arm/nuvoton/npcx to dts/arm/nuvoton.
So we will be chosen as reviewers automatically when dtsi files under
dts/arm/nuvoton are touched.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
A syscon device is a device managing a memory region containing a set of
registers that are not cohesive enough to represent as any specific type
of device. We need a driver for that because several other drivers could
use the same region at the same time and we need to io-map the region at
boot for MMU enabled platforms.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This patch add support for I2C on the Renesas R-Car.
This I2C hardware block can be found on various Renesas R-Car
SoC series.
It allows to perfom read and write on I2C buses in an
interrupt based way on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit adds a serial dummy driver compatible to vnd,serial.
This is needed that devices can access the uart device in tests
like tests/drivers/build_all/... .
Add myself as codeowner to avoid complicance check failure.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds the dts definitons for the seeed lora-e5 module.
Additionally I add myself as codeowner for the new dts/arm/seeed
directory.
This module packages a stm32wle5jc Sub-GHz Wireless Soc,
together with a 32MHz TCXO, a 32.768KHz crystal oscillator, and
power and RF circuitry.
With the introduction of lora support definitions for the radio
will be added in a future commit.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not enough time to review changes in these subsystems.
Propose to have VenkatKotakonda as KSCAN subsystem owner instead.
Adding SoC-specific driver owners.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add the code owner entries for all files related to the Xilinx GEM
Ethernet device driver.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
I cannot invest the time required for maintaining the networking
stack anymore, so I am stepping down from the maintainer role.
I am proposing Rober Lubos to be a new network maintainer.
I have been working with him for several years, and he is always
very helpful and knowledgeable to review and comment patches and
issues. He knows the network stack well and will for sure be able
to handle the task as he has been doing the maintenance already
for a long time.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Acked-by: Robert Lubos <robert.lubos@nordicsemi.no>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Convert the keyscan portion of the Holtek HT16K33 driver to adhere to
the kscan API instead of the GPIO API.
When this driver was introduced the kscan API was not present. The
keyscan driver was therefore implemented as a GPIO interrupt driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Adds @Thalley and @asbjornsabo (and the others
from the parent directory) to the babblesim audio
test directory.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This driver is for classic CAN, it makes use of CAN interface
in FIFO mode.
This driver support Standard ID as well as Extended ID.
Tested on H3ULCB, Ebisu platform, with external adapter and
in loopback mode.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Modify support for u-blox BMD-345-EVAL which uses the nRF52840
and a Skyworks RFX2411 FEM.
These edits follow the naming cnoventions that is used
with the other u-blox EVKs recently added, or in progress
This board is similar to the nRF52840dk_nrf52840 with the
addition of a FEM. Four Arduino GPIO pins have been
reassigned to the PA_LNA control pins.
u-blox would prefer to use this naming convention to match
other BMD-3xx-EVAL and EVK-NINA-Bx boards recently submitted.
Tested with blinky, button, and Bluetooth peripheral_hr
Checking dts files
Updated CODEOWNERS to rename bmd_345_eval to ubx_bmd345eval_nrf52840
Added CMakeLists.txt, updated board.c
Signed-off-by: Bob Recny <bob.recny@u-blox.com>
The cache API currently shipped in Zephyr is assuming that the cache
controller is always on-core thus managed at the arch level. This is not
always the case because many SoCs rely on external cache controllers as
a peripheral external to the core (for example PL310 cache controller
and the L2Cxxx family). In some cases you also want a single driver to
control a whole set of cache controllers.
Rework the cache code introducing support for external cache
controllers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch add support for polling based UART
on the Renesas R-Car SCIF (Serial Communication Interface
with FIFO)
This hardware block can be found on various Renesas R-Car
SoC series.
It allows to get console on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.
Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
- Move PM related APIs to `include/pm` so that it follows API `pm_`
prefix namespace. In order to make transition easier
`include/power/power.h` is kept pointing to `include/pm/pm.h`.
- Move most of device PM related content from `include/device.h` to
`include/pm/device.h` and `include/pm/runtime.h`.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds dictionary based logging support. Dictionary based
logging is binary based where one big difference is that
static strings are stored as pointers instead of the whole
string. This results in reduced space requirements for
storing log messages in certain scenairos.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).
INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move emul.h out of the top level include/ dir into
include/drivers/emul.h and deprecated the old location.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.
Controller can handle up to 32 GPIOs per banks.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add basic configuration for H3ULCB, just enough to see the
Zephyr boot banner on the ram console.
This configuration make use of the Cortex-R7 present on
r8a977951 SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add rak4631 board from RAKWireless based on nrf52840 and SX1262.
Board Documentation is completed
Signed-off-by: Guillaume Paquet <guillaume.paquet@smile.fr>
Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Armv8-R AArch64 MPU can support a maximum 16 memory regions, and the
actual region number can be retrieved from the system register(MPUIR)
during MPU initialization.
Current MPU driver only suppots EL1.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
According to Armv8-R64 Spec, MPU related meta data(region base/limit)
is 64 bits. So we need to re-define MPU related data structure here.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
It turns out that current known issues folder contains issues that are
no longer valid or present. I have searched for some of the regex
snippets listed but I have not been able to find any. Documentation was
the last active user of the known-issues folder, but has moved to
another solution.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
