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89383 commits

Author SHA1 Message Date
Anas Nashif afc319e3fa ztest: shell: add shell support
- Support for listing both testcases and testsuites
- Support for running single suites or single test cases
- Support shuffling tests and repeating execution based on command line
  arguments.

For example, build with

west build -p  -b qemu_cortex_m3  tests/kernel/sleep   -t run -- \
-DCONFIG_ZTEST_SHUFFLE=y -DCONFIG_ZTEST_SHELL=y

Following commands are available:

uart:~$ ztest
ztest - Ztest commands
Subcommands:
  run-all          :Run all tests
  shuffle          :Shuffle tests
  list-testsuites  :List all test suites
  list-testcases   :List all test cases
  run-testsuite    :Run test suite
  run-testcase     :Run testcase

shuffle accepts two arguments --suite_iter and --case_iter which allows
repeated exercution of testcases or suites.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-01-09 09:58:57 +01:00
Anas Nashif 6ba0e9c797 tests: sleep: reduce verbosity
Reduce verbosity and debug messages on the screen.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-01-09 09:58:57 +01:00
Anas Nashif 37529505ad ztest: remove old file
This c file is not being used anymore, so remove it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-01-09 09:58:57 +01:00
Gerard Marull-Paretas 14ff171411 soc: riscv: drop RISCV_PRIVILEGED_STANDALONE
This option is no longer needed, all SoCs have been moved out from
soc/riscv/riscv-privileged folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 724a967c1a soc: riscv: renove_virt: reorganize SoC folder
Move out from riscv-privileged, and convert to a standalone SoC.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 8729a782f9 soc: riscv: niosv: reorganize SoC folder
Move out of riscv-privileged, create new family for it.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas b5fb00bdc8 soc: riscv: opentitan: reorganize SoC folder
Remove from riscv-privileged, and create a standalone SoC.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 38a44e683e soc: riscv: sifive-freedom: reorganize SoC folder
Reorganized as follows:

- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)

Also moved out of riscv-privileged folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas b2b86556a7 soc: riscv: miv/mpfs: reorganize SoC folder
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.

[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
     fpga-and-soc-design-tools/mi-v

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 4c4beabecc soc: riscv: efinix-sapphire: reorganize SoC folder
Move things out from riscv-privileged, and convert to single SoC.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 7da6342dff soc: riscv: virt: reorganize SoC folder
Move out of riscv-privileged, and convert to single SoC (no
family/series).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas b7b19b8b05 soc: riscv: neorv32: reorganize SoC folder
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 7a44806a53 soc: riscv: s/litex-vexriscv/litex_vexriscv
To be consistent with other SoCs in the same folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 4a0d880350 soc: riscv: ite: reorganize SoC folder
Follow the vendor structure [1]:

- Family: ITE Embedded Controller SoCs
- Series: IT8XXX2
- SoCs: IT81202BX, IT81202CX, etc.

[1]: https://www.ite.com.tw/en/product/category?cid=1

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 8027689392 soc: riscv: andes_v5: reorganize SoC folder
Split out from riscv-privileged folder, and create a new family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 87f3b07292 soc: riscv: starfive_jh71xx: reorganize SoC folder
Move it out from RISC-V privileged folder, and create a standalone
family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 5a98d87335 soc: riscv: gd32vf103: reorganize SoC folder
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 72e52a06aa soc: riscv: telink_b91: reorganize SoC folder
Reorganize following the hierarchy found in the vendor website [1]:

- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518

Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].

[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
     B91_Generic_Starter_Kit_Hardware_Guide/

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas d8c0cc2e35 soc: riscv: introduce temporary RISCV_PRIVILEGED_STANDALONE
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 0106e8d14c arch: riscv: introduce RISCV_PRIVILEGED
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.

Note that the SoC family naming scheme will be fixed in upcoming
commits.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 9a35ad858c soc: riscv: gd32vf103: move nuclei CSR header
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas 6443c50bd0 soc: riscv: move privileged code to common folder
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Adrien Ricciardi 4824e405cf drivers: i2c: i2c_dw: Fixed integer overflow in i2c_dw_data_ask().
The controller can implement a reception FIFO as deep as 256 bytes.
However, the computation made by the driver code to determine how many
bytes can be asked is stored in a signed 8-bit variable called rx_empty.

If the reception FIFO depth is greater or equal to 128 bytes and the FIFO
is currently empty, the rx_empty value will be 128 (or more), which
stands for a negative value as the variable is signed.

Thus, the later code checking if the FIFO is full will run while it should
not and exit from the i2c_dw_data_ask() function too early.

This hangs the controller in an infinite loop of interrupt storm because
the interrupt flags are never cleared.

Storing the rx_empty empty on a signed 32-bit variable instead of a 8-bit
one solves the issue and is compliant with the controller hardware
specifications of a maximum FIFO depth of 256 bytes.

It has been agreed with upstream maintainers to change the type of the
variables tx_empty, rx_empty, cnt, rx_buffer_depth and tx_buffer_depth to
plain int because it is most effectively handled by the CPUs. Using 8-bit
or 16-bit variables had no meaning here.

Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
2024-01-08 20:57:05 -06:00
Daniel Leung 2ab367d149 x86: ia32/gdbstub: remove dead code
There is logically dead code which will never run. So remove.

Fixes #66848

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-01-08 20:54:16 -06:00
Fabio Baltieri a006ad5399 ci: do_not_merge: check for dev and arch review labels as well
Add "Architecture Review" and "dev-review" to the list of labels that
block a PR from merging, less chances to merge these before discussion
unintentionally.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-01-08 15:03:04 -05:00
Reto Schneider 698f3b1a58 doc: Fix sentence
Before this commit, the sentence did not make sense.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
2024-01-08 14:06:40 -05:00
Flavio Ceolin 3267bdc4b7 fs: fuse: Avoid possible buffer overflow
Checks path's size before copying it to local variable.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-01-08 13:29:19 -05:00
Håvard Reierstad 9c3ca4573a bsim: Bluetooth: Mesh: Add gatt suspension test
Adds two test-cases to `test_suspend.c`, both checking that gatt
advertisement is stopped when suspending Mesh, and that is started again
when Mesh is resumed.

The first test-case involves suspending and resuming Mesh, and
the second test-case involves suspending Mesh and disabling Bluetooth,
then re-enabling Bluetooth and resuming Mesh.

Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
2024-01-08 13:21:58 -05:00
Håvard Reierstad 6c5fc658ef Bluetooth: Mesh: suspend/resume gatt advs
Disables pb gatt- and gatt proxy advs when suspending Mesh, and
enables them again when resuming Mesh.

Adds `bt_mesh_adv_gatt_send` to `bt_mesh_resume` to make sure that
GATT advs start after resumption.

Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
2024-01-08 13:21:58 -05:00
Håvard Reierstad 9285ea3238 Bluetooth: Mesh: fix proxy srv return value
Previously, `bt_mesh_proxy_gatt_enable` returned the return value from
`k_work_schedule`, which could be a positive (non-error) message.
Now, it only returns negative error codes (else 0).

Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
2024-01-08 13:21:58 -05:00
Håvard Reierstad 0480367d77 bsim: Bluetooth: Mesh: refactor suspend test
Renames tx to DUT and rx to Tester to clarify roles in test.

Re-uses the same body for suspend/resume and suspend/disable/resume
for DUT with a parameter to toggle disabling BT.

Re-uses the same Tester config in both existing test-cases as the
previous configs were duplicates.

Updates the dut suspension status in the message handler.

Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
2024-01-08 13:21:58 -05:00
Håvard Reierstad ee337087fa bsim: Bluetooth: Mesh: extract common adv logic
Extracts logic related to waiting for packets from
`test_advertiser.c` and `test_beacon.c` to use in a sync mechanism.
Introduces a sync mechanism in bsim with the functions
`bt_mesh_test_send_over_adv` and `bt_mesh_test_wait_for_packet`

Extracts gatt-related logic from `test_advertiser.c` into a separate
file so it can be re-used.

Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
2024-01-08 13:21:58 -05:00
Marc Herbert 4aa0e7af68 west: sign.py: add "REM" support to pass comments through cpp
Generated outputs can be difficult to read, preserving comments helps a
lot and they often provide good `git grep` search keywords.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2024-01-08 13:20:41 -05:00
Marc Herbert a27e8f9a19 west: sign.py: explain why -P is passed to cpp
Zero-functional change.

Also move it to a separate line so it's more convenient to temporarily
comment it out.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2024-01-08 13:20:41 -05:00
Marc Herbert 2ee6c26d15 west: sign.py: rename new generated/platf.toml to rimage_config.toml
CMake-based build systems like Zephyr's use separate build directories;
one for each build configuration. Even Zephyr's multi-build system
"sysbuild" (which is not relevant here) uses separate subdirectories.

So there is only one pre-processed, .toml file generated by build
directory and no need to vary its filename based on the platform name or
any other configuration parameter. It can and should keep the same
filename across build directories as zephyr.elf and all other build
artefacts do.

Moreover, when building a collection of configurations (as for instance
`sof/scripts/xtensa-build-zephyr.py` does), keeping all build
directories consistent with each other simplifies installation,
checksumming and any other post-processing.

"Fixes" recent commit 15336045af ("west: sign.py: generate platf.toml
from platf.toml.h with cc -E")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2024-01-08 13:20:41 -05:00
Chun-Chieh Li fe75bb950f shields: esp_8266: support Nuvoton numaker_pfm_m467 board
1. Support H/W reset pin
2. Support UART flow control (CTS/RTS)

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
2024-01-08 16:18:38 +00:00
Yong Cong Sin c7ce871a04 tests: exclude renode from tests requiring unsimulated peripherals
Physical boards work on these tests but some of the required
peripherals are not simulated by `renode`, executing the tests
with renode-simulated board in CI will fail.

Exclude `renode` simulation from these tests.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 16:17:43 +00:00
Yong Cong Sin fa5cb1afa8 boards: hifive_unmatched: add renode simulation
Changes to this file were missed out from the original
PR #65564 that added Renode support for this board, add them
here so that it gets ran in CI.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 16:17:43 +00:00
Jun Lin 34b9b3aaca dts: npcx: sha: fix the incorrect unit address
Fix the incorrect unit address of sha node from 13C to 148 to avoid
the build warning.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-01-08 16:17:17 +00:00
Fabio Baltieri e0c24c8842 doc: input: few minor fixes
Few documentation fixes that got caught post merge.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-01-08 16:16:26 +00:00
Manuel Argüelles c68564bc93 boards: arm: ucans32k1sic: enable FlexCAN
Enable FlexCAN peripheral driver for ucans32k1sic board. The GPIO-based
CAN transceiver driver is used to control the on-board CAN transceivers.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-08 08:30:49 -06:00
Manuel Argüelles fa0b1b5fe8 drivers: can: flexcan: add support for S32K1xx
Add message buffer allowed values for S32K1xx devices. Except S32K14xW
parts which supports 64 MBs, the rest of the parts support a maximum of
32 MBs.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-08 08:30:49 -06:00
Manuel Argüelles 58f5720eb4 dts: arm: nxp: add FlexCAN support for S32K1xx
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-08 08:30:49 -06:00
Karol Gugala 133d8c7817 boards: efm32pg_stk3401a: uart: switch to new pinctrl API
The board uses pinctrl API. This commit updates pin USART pin definition
to be compliant with new API.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2024-01-08 15:10:03 +01:00
Karol Gugala 57238057f0 boards: efm32gg_sltb009a: uart: switch to new pinctrl API
The board uses pinctrl API. This commit updates pin USART pin definition
to be compliant with new API.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2024-01-08 15:10:03 +01:00
Sylvio Alves 617b45ab59 west.yml: update hal_espressif to fix libc calls
Make sure some ROM libc calls are weak to allow
Zephyr's libc implementation instead.

Fixes #66351

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-01-08 15:09:48 +01:00
Sylvio Alves b19c164e7b soc: espressif: add common linker tls entry
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-01-08 15:09:48 +01:00
Yuval Peress 5edc45421a icm42688: Capture the spi return value
Handle the return value of the spi transaction.

Fixes #58582

Signed-off-by: Yuval Peress <peress@google.com>
2024-01-08 15:09:42 +01:00
Yuval Peress 3f2d6efc9c icm42688: Remove unnecessary locks
The entire switch statement is already wrapped in a lock which is
acquired just before configuring the gpio pin.

Signed-off-by: Yuval Peress <peress@google.com>
2024-01-08 15:09:42 +01:00
Bartosz Bilas 9618b761ec dts: bindings: max20335: add regulator-init-microvolt/microamp to allowlist
This PMIC can handle those features, so let's add them.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2024-01-08 15:09:35 +01:00