Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This removes all occurrences of arm,num-mpu-regions relying on the value
reported by the register instead.
A user may still define this property if they need to have a compile time
definition for it.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Remove temp-, vref- and vbat-channel from STM32 ADC nodes as it is not
used in the driver anymore.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add new vref node to the DTS definitions of supported SoCs.
Extend DTS ADC channel properties where missing.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
In all STM32 dts, remove all reference to the following properties:
- has-temp-channel
- has-vref-channel
- has-vbat-channel
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that we have a binding to define the channel number for temperature
and Vref measurement, update all dtsi to include the information.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove the vref-mv = <3300>; property for all the ADC node of
the stm32 devices as it is set by default to 3300mV by the
dts/adc/st,stm32-adc.yaml
(Except for the stm32f303 vref is 3000mV)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Provide SDMMC domain clock, when required (because it is common)use
the same as the one selected by USB and RNG.
Otherwise, when available use HSI48, otherwise use the most handy (MSI,
sysclk ...).
PLLSAI is not used as not implemented for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Describe USB default domain clock on all USB devices.
When available select HSI48.
On some series, a default clock my be set by default at start up.
On those series, in order to be able to compute USB clock at runtime,
clock_control driver needs to be aware of configuration and then this
default config has to be described explicitly too.
Default clocks are not enabled though. It is up to board configuration
to provide correct clock configuration (and we should not enabled by
default clocks that would not be required by board configuration).
Note: This change doesn't consider STM32F1/F3 devices, which
have a specific USB clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
zephyr.dts:482.21-491.5: Warning (simple_bus_reg): /soc/dietemp: missing
or empty reg/ranges property.
To fix this bug, just move dietemp node outside of soc{}.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
Add the support of the temperature sensor in the ADC device-tree node of
each stm32 where it is available.
- Check all the ADC of the stm32 mcus where the temp and VrefInt monitoring
is available (based on the Ref Man).
- Check that has-temp-channel; and has-vref-channel; in the corresponding
ADC node of the DTS of each stm32 mcu is correctly set.
- Verify the VTEMP/ VREFINT activation in the in adc_stm32.c for example).
-Add the die-temp node (based on the ref man/ datasheet).
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
The nist-config and health-test-magic properties are added
to the dtsi file, in the RNG node for the stm32 devices
that supports the RNG entropy source validation.
The health-test-magic nb exists on stm32l552 stm32h723/7a3.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The definition of the octospi clock source is given
by the DTS node. The default value selects the sysclk
(not pclk) for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
According to the formulas found in the reference manuals of the SoC
families using the "st,stm32-temp-cal" version of the temperature sensor
(i.e. G0, G4, H7, L0, L1, L4, L5, U5, WB, WL), the temperature is
computed with the following formula:
T = ((TS_CAL2_TEMP - TS_CAL1_TEMP) / (TS_CAL2 - TS_CAL1))
* (TS_DATA - TS_CAL1) + TS_CAL1_TEMP
What is called ts-cal-offset in the stm32_temp driver is therefore the
same value as TS_CAL1_TEMP1. Use it directly instead of defining another
property.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Set the priority of the wwdg instance to 6
else a build error happens :
static assertion failed: "Invalid interrupt priority.
Values must not exceed IRQ_PRIO_LOWEST"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32 supports now custom PWM flags, include them by default as done for
the standard flags.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce ADC properties which indicated if the ADC instances have
dedicated channels for the internal temperature sensor or voltage
reference.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This PR adds the different handling of temperature sensor for the
STM32L5 soc. In this soc, there are some calibration settings which
need to be applied for temperature conversion.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Note: on stm32h7 not all product lines support this configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
