Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I2faa823226cd76d129d2bc3db961c9b862aaf784
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
zedboard_pulpino
1) has a 16750 uart, which is compatible with the uart_ns16550 driver.
2) make use of the pulpino timer driver
Change-Id: Ifda710fc8dea547ada05bb42e604d7cfdff284d5
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver
Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
tested with blinky, button and disco apps
Change-Id: I4b520d4f3e42c97e4a723747ce4a6c67ca9f1d18
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added USED_RAM_SIZE and MAX_HEAP_SIZE definitions for
SOC_RISCV32_QEMU and SOC_RISCV32_PULPINO.
Otherwise, not passing sanitycheck
Change-Id: Ia32b12e1694dc472e9f7f9eb10c5f2e12e928c3a
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
riscv-qemu UART:
1) comprises only one register that is used to send or
receive characters in a polling fashion.
2) does not have a FIFO and is not interrupt-driven.
Change-Id: I9408f1776eba4cec4aa203a5da759ec04bcddf1f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The riscv-qemu timer driver does not implement
TICKLESS_IDLE
Change-Id: I3eeb5abb05b3f16b55ab9343c2045295b3010cfd
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The pulpino_timer driver does not implement TICKLESS_IDLE
for the time being.
Change-Id: I0cce8c8a7e203d551a924863462e6c86af4c98ff
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)
Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Default 256 bytes stack size for idle task is not enough, as
stack grows/shrinks by a multiple of 16-bytes in the
RISC-V architecture.
Increase it to 512 bytes for RISCV32 architecture
Change-Id: I8321c48e4c1a877b252ba5561f3cbdd1fe475fc7
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added _MOVE_INSTR for RISCV32 architecture
The store instruction has a different syntax in RISC-V,
compared to the other architectures. Hence, for each
architecture, specify the entire load instruction within
the _MOVE_INSTR variable.
Change-Id: Iedc421e73411876abd8b698f7d4b46081b473d79
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Compiling Zephyr with an external riscv32 toolchain would
require the following env variables to be exported:
export ZEPHYR_GCC_VARIANT=riscv32
export RISCV32_TOOLCHAIN_PATH=/PATH/TO/TOOLCHAIN/BINARY
Change-Id: I2072ed9079a4cabd27837ab39b947bc0a0a1a8b4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Force-align all variables defined via asm .word to ensure 4-byte
alignment.
The straddled_tick_on_idle_enter variable was a bool, which resolved in
an one-byte quantity. Changing it to a 32-bit integer. It would have
occupied 4 bytes anyway with alignment.
Fixes ZEP-1549.
Change-Id: If5e0aa1a75dbc73d896b44616f059d221fe191c6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Update these scripts to explicitly call out python version 2. Some
distributions have started making /usr/bin/python version 3, and other
distros have expressed a desire to do the same.
Also use the
#!/usr/bin/env python2
construct instead of an explicit path so that the user can more easily
use their own python install by just placing it earlier in the path
Jira: ZEP-1548
Change-Id: I36dccc652353ba8bd58c483dba3ce61d3643de00
Signed-off-by: David Brown <david.brown@linaro.org>
At least one Linux distribution (Arch) has made python 3 the default
interpreter, and Debian and Ubuntu have expressed a desire to eventually
make this the case. As such, invoking 'python' or '/usr/bin/python'
will possibly run python 3 instead of version 2.
Distributions have included a 'python2' link for quite some time now,
and given that we have some scripts that require python 3, we should be
explicit about those that require python 2.
In addition, be more consistent about how python is invoked, preferring
the:
#!/usr/bin/env python2
construct rather than a hardcoded path to python. This allows the user
to have an alternative python in their path that will be used in
preference to the system provided version.
Jira: ZEP-1548
Change-Id: I125c2af808dc268f74277bc97a092df3acad23c0
Signed-off-by: David Brown <david.brown@linaro.org>
The commit verify below PWM apis
pwm_pin_set_cycles()
pwm_pin_set_usec
test PWM apis under always-on, half-on and alway-off modes
Change-Id: I2251be23ad9c443703dac44e138651a63d2d7211
Signed-off-by: jing wang <jing.j.wang@intel.com>
The mcux pinmux driver enables the port clocks, so the soc init no
longer needs to enable them. Also removes some soc defines that were
used only by the legacy k64 pinmux driver.
Change-Id: I63174bef4024b5a09a73f941cea0aec691c759d3
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The k64 pinmux driver was deprecated when the more generic mcux pinmux
driver was added, but it can actually just be removed because it is not
a public interface. Applications should be using the public pinmux API,
not the private k64 pinmux API. There was one case in the net samples
that used the private API which was cleaned up in a previous patch.
Change-Id: I49a6397baa57973930cb63bd2a9883b14f7ddafd
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we have a more generic mcux gpio driver that can be used across
multiple Kinetis SoCs, remove the specific k64 gpio driver.
Jira: ZEP-1394
Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Sample projects that pair the frdm_k64f board with a cc2520 require
additional pinmux settings beyond the standard frdm_k64f pinmux. These
settings used the private k64 pinmux API rather than the public pinmux
API.
Because the mcux pinmux driver now always supports the public pinmux API
(vs. the k64 pinmux driver which only supported it in pinmux dev mode),
we can convert the frdm_k64f_cc2520 projects to use the public pinmux
API and the mcux pinmux driver.
Change-Id: Idfae8393171b007d8629e34bfae64255f55c6792
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Stop using the specific k64 gpio driver by default and start using the
more generic mcux gpio driver instead.
Jira: ZEP-1394
Change-Id: I54ec9b62cc8790b8973efc34fa36d17da523971e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new mcux gpio driver that can be used for k64 and other Kinetis
SoCs. This driver uses mcux CMSIS register accesses to the GPIO and PORT
modules. Some of the logic from the k64 gpio driver was reused and
refactored (mainly flag parsing and callback handling).
Jira: ZEP-1394
Change-Id: If5e9390861c181ec555dce6569b14debb729526a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The k64 gpio driver quietly initializes the pinmux to force the pin to
be a gpio, regardless of the setting defined by the board's pinmux
table, or even if the pin was not in the pinmux table.
This behavior caused the accelerometer interrupt pin to be incorrectly
defined in the frdm_k64f and hexiwear_k64 pinmux tables.
Change-Id: If46df0e051452fef291d5ad5cdff56463d5f465e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The hexiwear_k64 i2c pinmux settings were copied over incorrectly when
the new mcux pinmux driver was created.
Change-Id: I72e5f8f7c06e2d9b08921109691edaf311f3811b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the uart console pins from the k64 soc init to the frdm_k64f and
hexiwear_k64 board pinmux tables. Not having these pins in the board
pinmux tables led one to believe that no pins in PORTB were being used
on the hexiwear_k64 board, and thus the port was incorrectly disabled by
default.
Also fixes PORTB to be enabled by default if the uart console is used.
Change-Id: Ide6b7b34dfba8a75a02a8f2bf37cce843afb92f1
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Changes the init level for the mcux pinmux driver from POST_KERNEL to
PRE_KERNEL_1. This will allow moving the uart console pins from the k64
soc init to the board pinmux tables.
Change-Id: I6d3377c9a689c12711c84387f74843ca9488df52
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch provides initial support for the SoC STM32F107. This SoC
belongs to the Connectivity Line devices.
Connectivity line family incorporates up to 14 communication
interfaces such as: 2 x I2C, 5 x USART, 3 x SPI, 2 x CAN, USB 2.0,
10/100 Ethernet MAC.
Change-Id: I5cb2c458bce9ec1558b4168e87a7003ad9f606a5
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all the ksdk/mcux shim drivers use the config HAS_MCUX, we can
remove the config HAS_KSDK.
Change-Id: I94b7db41efae10c9234681aeb57f94e67a33c262
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the ksdk random generator shim driver to mcux.
Change-Id: I8bc376937fed3024c809782139a0a72c7332f89a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
