Commit graph

63866 commits

Author SHA1 Message Date
Gerard Marull-Paretas c7b5b3c419 samples: migrate includes to contain <zephyr/...> prefix
In order to bring consistency in-tree, migrate all samples to the use
the new prefix <zephyr/...>. Note that the conversion has been scripted:

```python
from pathlib import Path
import re

EXTENSIONS = ("c", "h", "cpp", "rst")

for p in Path(".").glob("samples/**/*"):
    if not p.is_file() or p.suffix and p.suffix[1:] not in EXTENSIONS:
        continue

    content = ""
    with open(p) as f:
        for line in f:
            m = re.match(r"^(.*)#include <(.*)>(.*)$", line)
            if (m and
                not m.group(2).startswith("zephyr/") and
                (Path(".") / "include" / "zephyr" / m.group(2)).exists()):
                content += (
                    m.group(1) +
                    "#include <zephyr/" + m.group(2) +">" +
                    m.group(3) + "\n"
                )
            else:
                content += line

    with open(p, "w") as f:
        f.write(content)
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:29:59 +02:00
Anas Nashif 8d41af0536 doc: update architectures in README
Add all missing architectures to the README.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-05-06 11:29:28 +02:00
Anas Nashif 0f64fdfbfd action: doc: use doxygen 1.9.4
1.9.2 distribution does not exist any more. Use the 1.9.4 which is the
latest.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-05-06 09:19:46 +09:00
Ederson de Souza ddb779e31d soc/xtensa/intel_adsp/tools: Make cavstwist.sh accept ssh port
Sometimes the remote ssh server is not on default port. This patch makes
cavstwist.sh accept an ssh port in the host address: host[:port].

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-05-05 17:00:31 -04:00
Yonatan Schachter 29677da91f rpi_pico: Fix compilation for non Linux systems
On non Linux system, the compilation failed because the main
CMake did not pass the CMAKE_SYSTEM_NAME to the bootloader's
CMake. This caused the variable to be empty, instead of being
"Generic".

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-05-05 14:47:23 -05:00
Sjors Hettinga 11288cdbdd tests: net: socket: tcp: Make test_vX_msg_waitall more robust
The close function on a TCP socket can return before the complete
socket has been closed, as there might be packets still in flight.
Add a wait at the end of the test so we are sure all sockets have
been closed before the next test starts.

Signed-off-by: Sjors Hettinga <s.a.hettinga@gmail.com>
2022-05-05 14:45:02 -05:00
Sjors Hettinga cf3466ff74 tests: net: socket: tcp: Make test_open_close_immediately more robust
The close function on a TCP socket can return before the complete
socket has been closed, as there might be packets still in flight.
Modify the test to wait briefly (less then the retransmit time), before
counting the number of still open net_contexts. This makes the test
outcome not dependent on the scheduling order of the different tasks.

Secondly the test actually checks the number of open contexts to be zero
so there is no need to wait for any open contexts to still close.

Signed-off-by: Sjors Hettinga <s.a.hettinga@gmail.com>
2022-05-05 14:45:02 -05:00
Sjors Hettinga 40ee401dd2 tests: net: socket: tcp: Add test to validate connect timeout
When there is no response from the server, a client side connect
should return a ETIMEOUT. This tests breaks the connection and validates
this behavior.

Signed-off-by: Sjors Hettinga <s.a.hettinga@gmail.com>
2022-05-05 14:45:02 -05:00
Herman Berget 5b0deb058b Bluetooth: Host: Remove unused nfy_mult_data
After adding the more general ATT meta data, it is no longer used.

Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
2022-05-05 14:42:38 -05:00
Piotr Pryga fecc193630 tests: Bluetooth: df: Enable refactored LLCPs for df conn test
There was missing kconfig option that enables refactored LLCPs.
That caused build error in Direction Finding connection_cte_tx_params.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2022-05-05 14:41:59 -05:00
Piotr Pryga ccbe5a56e8 tests: Bluetooth: df: Fix ref to renamed ll_scan_set member
The ll_scan_set::per_sync was renamed to ll_scan_set::periodic.
Direction finding connectionless_cte_rx test didn't build.

The commit fixes the issue.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2022-05-05 14:41:59 -05:00
Herman Berget 29e3188703 Bluetooth: Tests: Mark test scripts as executable.
The mode change was showing up in the git diff after running all bsim
tests.

Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
2022-05-05 14:40:21 -05:00
Herman Berget 51dde9e87a Bluetooth: Tests: Reduce simulation time for L2CAP test
The test was running for unnecessarily long.

Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
2022-05-05 14:40:21 -05:00
Rubin Gerritsen b51353628a Bluetooth: Controller: DF configs should not depend on BT_LL_SW_SPLIT
None of the common DF configs should depend on using BT_LL_SW_SPLIT.
Added dependencies to it where this was the case.

Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
2022-05-05 14:39:04 -05:00
Rubin Gerritsen aec5307ac9 Bluetooth: Controller: Make some DF configs specific to BT_LL_SPLIT
These configurations are tighlty coupled to the implementation,
so these should be hidden when not using BT_LL_SW_SPLIT.

Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
2022-05-05 14:39:04 -05:00
Rubin Gerritsen b25a2fab79 Bluetooth: Controller: Make it possible to support only TX or RX DF
Some controllers may support only TXing or RXing CTE.
As all DF features are guarded by BT_CTLR_DF, we need to ensure
that it is possible to select those when only TX or RX is available.

Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
2022-05-05 14:39:04 -05:00
Rubin Gerritsen e51999e661 Bluetooth: Controller: Document the purpose of BT_CTLR_DF_SUPPORT
I believe it will now be easier to understand how to use it.

Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
2022-05-05 14:39:04 -05:00
Georgij Cernysiov 1520820bff drivers: pwm: stm32: fix PWM channel disabling
Move period and pulse computation to right before
the channel enable code.

That fixes the inability to disable the channel by
providing the period of 0.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-05-05 14:36:56 -05:00
Peter Maxwell Warasila d875cfc110 dts: arm: st: u5: add fdcan to stm32u5 series
Add support for the fdcan peripheral to the stm32u5 series device tree
include. This can be applied here since (at present) all of the stm32u5
series MCUs have an FDCAN peripheral.

Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
2022-05-05 14:35:37 -05:00
Peter Maxwell Warasila c91a70e130 driver: can: stm32fd: add stm32u5 clock selection
The STM32u% series of processors has a unique set of clock sources for
the FDCAN peripheral. This brings the selection in line with the
existing can_stm32fd clock selection Kconfigs.

This change was tested on a proprietary board using the STM32U5 series
which exposes the CAN pins of the SOC using a transciever on a live CAN
bus as well as on the nucleo_g474re board from ST in loopback mode.

HSE and PLL1Q tests run and all passed.

PLL2P is not currently supported by the clock drivers for STM32U5, and
as such is currently untested. When this support is added, the driver
should be able to use this clock without issue.

When changes from #42097 are merged this fix should be deprecated in
favor of using the methods outlined there.

Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
2022-05-05 14:35:37 -05:00
Gerard Marull-Paretas 40c59da65c doc: hardware: pinctrl: inform about /omit-if-no-ref/
Update the documentation to inform about /omit-if-no-ref/ when using the
node-based approach.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:33:06 -05:00
Gerard Marull-Paretas b1ae0b6bd1 boards: arm: nucleo_g0b1re: update pinctrl node file
The file with pinctrl nodes has been updated to
st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi for this board.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:33:06 -05:00
Gerard Marull-Paretas 6c547229dc manifest: update hal_stm32 revision
Pull latest pinctrl changes:

- Updated to CubeMX 6.5.0 database
- All nodes are prefixed with /omit-if-no-ref/

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:33:06 -05:00
Gerard Marull-Paretas 6be97b00fd dts: arm: microchip: mec127x: add /omit-if-no-ref/ to pinctrl nodes
All DT nodes end up being part of the generated 'devicetree_unfixed.h'
header, wether they are referenced or not. The number of entries in that
file can grow quickly when using pre-generated pinctrl nodes.
Considering <devicetree.h> (file uncluding devicetree_unfixed.h) is used
in lots of places nowaday, not using /omit-if-no-ref/ can lead to
increased build times.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:33:06 -05:00
Krzysztof Chruscinski 4b4c5bfcee lib: os: cbprintf: Fix variable assignment
When in_len is 0 then length is calculated from the package and
assignment was missing.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-05-05 14:29:26 -05:00
Gerard Marull-Paretas 8c2a732067 types: mode to include/zephyr
With the new <zephyr/> include prefix, the "types" header ended up being
located in <zephyr/zephyr/types.h>, ie weird. Code that hasn't migrated
to <zephyr/zephyr/types.h> (no occurences in tree) will be automatically
prepared for the removal of the legacy include path. Most applications
will not be impacted as both include and include/zephyr are now in the
include path, and they'll be already prepared for the future.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:26:05 -05:00
Gerard Marull-Paretas bad523d1aa arch: x86: zefi: support multiple include paths
When legacy mode is enabled, Zephyr includes both include/ and
include/zephyr. Allow the zefi.py script to accept multiple include
paths to cover this scenario.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-05 14:26:05 -05:00
Evgeniy Paltsev 1cfd4fdc24 ARC: boards: hsdk_2cores: allow mwdt toolchain usage
Allow mwdt toolchain usage for 2 cores HSDK configuration
as we have it for 4 cores configuration.

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2022-05-05 14:23:57 -05:00
Henrik Brix Andersen 0acb154863 soc: riscv: openisa: rv32m1: remove default pinmux configuration
Remove the default pinmux Kconfig configuration from the OpenISA RV32M1
SoC.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 191bf2ab0a boards: riscv: rv32m1_vega: convert from pinmux to pinctrl
Convert the OpenISA RV32M1 VEGAboard from pinmux to pinctrl.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 64c9fadc7c drivers: pwm: rv32m1: tpm: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 TPM PWM driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen c83a0d5d1f drivers: spi: rv32m1: lpspi: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 LPSPI SPI driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 7b33d4af6c drivers: i2c: rv32m1: lpi2c: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 LPI2C I2C driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 738e9f57f9 drivers: serial: rv32m1: lpuart: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 LPUART serial driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 9ba953d13a drivers: gpio: rv32m1: configure pin mux as GPIO
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin. This removes the need to explicitly call pinmux_pin_set() in board
code.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen a1181dbd16 dts: riscv: rv32m1: add dummy pinctrl node
The OpenISA RV32M1 pinctrl groups need a dummy pinctrl node to populate
with pinctrl options at the board level.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 1dc3b237fa drivers: pinctrl: add OpenISA RV32M1 pinctrl driver
Add OpenISA RV32M1 pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen db643ea610 dts: bindings: pinctrl: add pinctrl binding for OpenISA RV32M1
Add pinctrl devicetree bindings for the OpenISA RV32M1.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen 2e9d7dd70d soc: riscv: openisa: rv32m1: add pinctrl header file
Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Anas Nashif d8b45e38c1 MAINTAINERS: add DAI area
Add new area with juimonen as the maintainer.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-05-05 11:00:30 -04:00
Arsen Eloglian 0a2df833f9 dts: add binding for intel ssp
Add ssp (sspbase) node for Intel ssp.

Signed-off-by: Arsen Eloglian <ArsenX.Eloglian@intel.com>
2022-05-05 08:47:03 -05:00
Bradley Bolen dfc4c3f8a6 soc: arm: xilinx_zynqmp: Enable the VFP
This SoC supports vfpv3-d16 with single and double precision and 16
64-bit registers.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Bradley Bolen 88ba97fea4 arch: arm: aarch32: cortex_a_r: Add shared FPU support
This adds lazy floating point context switching.  On svc/irq entrance,
the VFP is disabled and a pointer to the exception stack frame is saved
away.  If the esf pointer is still valid on exception exit, then no
other context used the VFP so the context is still valid and nothing
needs to be restored.  If the esf pointer is NULL on exception exit,
then some other context used the VFP and the floating point context is
restored from the esf.

The undefined instruction handler is responsible for saving away the
floating point context if needed.  If the handler is in the first
irq/svc context and the current thread uses the VFP, then the float
context needs to be saved.  Also, if the handler is in a nested context
and the previous context was using the FVP, save the float context.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 80bd814131 arch: arm: cortex_r: Initialise VFP D32 registers for DCLS
This commit updates the Cortex-R reset routine to initialise
(synchronise) the VFP D16-D31 registers when Dual-redundant Core
Lock-step (DCLS) is enabled.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00
Bradley Bolen 7f44e28619 arch: arm: aarch32: Create z_arm_floating_point_init() for Cortex-R
This will enable the VFP unit on boot to handle the case where
FPU_SHARING is not enabled.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Bradley Bolen 7c1e399179 arch: arm: aarch32: Create a fpu stack frame
Grouping the FPU registers together will make adding FPU support for
Cortex-A/R easier later.  It provides the ability to get the sizeof and
offsetof FPU registers easier.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Bradley Bolen 3f7162fc07 arch: arm: aarch32: Rearrange exception stack frame
Cortex-A/R use a descending stack frame and the hardware does not help
with the stacking.  This led to some less than desirable workarounds in
the exception code where the basic stack frame was saved twice.
Rearranging the order of the exception stack frame removes that problem
and provides a clearer path to saving CPU context in a fully descending
manner.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 18398948db cmake: gcc: target_arm: Force FP hard ABI for DCLS
When Dual-redundant Core Lock-step (DCLS) topology is used, the VFP
registers across the two redundant cores must be manually initialised
and synchronised, and this requires the `-mfloat-abi=hard` option to
be specified.

This commit forces the use of FP "hard" ABI on the VFP-equipped cores
that are configured in DCLS topology.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 6d4bce81ae cmake: gcc: target_arm: Support advanced floating-point options
This commit updates the Zephyr build system to support specifying
advanced floating-point compilation options derived from the newly
introduced unified floating-point configurations.

The following changes are introduced by this commit:

1. Specify architecture floating-point option to the `-mcpu` flag.
2. Specify floating-point unit (FPU) type using the `-mfpu` flag.

Note that the `-march` flag is not specified separately because the
`-mcpu` flag provides more detailed architecture options and this
makes the `-march` flag redundant.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 5181c61797 arch: arm: Add unified floating-point configuration symbols
This commit adds the unified floating-point configuration symbols for
the ARM architectures.

These configuration symbols allow specification of the floating-point
coprocessors, such as VFP (also known as FP for Cortex-M) and NEON,
for the ARM architectures.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00