Commit graph

110 commits

Author SHA1 Message Date
Marc Herbert 68c1cafb41 intel_adsp: dts: ace: lower case 71C00 to fix DTC warning
Fixes the warning below. This commit does not change the firmware
binary. Thanks Kumar Gala for the suggestion.

  build-mtl/zephyr/zephyr.dts:279.42-285.5: Warning (simple_bus_reg):
  /soc/ace_comm_widget@71C00: simple-bus unit address format error,
  expected "71c00"

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-03-07 08:33:30 +01:00
Adrian Warecki 55be5d81f2 ace: dts: Add watchdog device to the device tree
Added watchdog devices to the device tree of mtl platform.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:42:52 -05:00
Adrian Warecki 8794de2934 intel_adsp: soc: ace: Add communication widget driver
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-01-18 10:47:21 +01:00
Jaska Uimonen a9b3d93550 intel_adsp: dai: Add support for ALH up to 16 nodes
ALH dts definitions need to have 16 nodes, thus add them to supported
platforms (cavs25 and ace15).

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-01-17 13:06:39 -05:00
Tomasz Leman 73feb35e99 ace: dts: gpdma: add third controller
Meteorlake has three GPDMA controllers.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-21 10:11:41 +01:00
Jakub Dabek d76419973a devicetree: add virtual memory entry for intel platform
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h

Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
2022-12-20 07:03:55 -05:00
Serhiy Katsyuba 9cf89603df intel_adsp: dai: Add support for ALH streams 2 and 3
Adds two additional alh2 and alh3 "devices" to already defined
alh0 and alh1. This (seems) is a temporarily solution as
the hardware actually supports 16 streams and future update
to device tree is required.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2022-12-17 06:47:55 -05:00
Tomasz Leman d9432ebcb9 ace: dts: hda: add power domain
Assigning power domain to the HDA DMA.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-16 11:03:15 +00:00
Tomasz Leman ff01458111 ace: dts: gpdma: add power domain
Assigning power domain to the GP DMA.

NOTE: Only controllers 1 and 2 are under IO_0 domain, controller 0 is
      under HUB-ULP domain.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-15 19:17:21 +01:00
Kai Vehmanen 2dd4cbc755 dts: xtensa: intel: update cavs25_tgph to match cavs25
Add definitions for DMAs, Digital Audio Interfaces (DAIs) and
the necessary clocks to enable full use of audio peripherals
in the intel_adsp_cavs25_tgph boards.

Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-12-07 10:36:34 -05:00
Tomasz Leman 6052d9d1e6 ace: dts: dmic: add power domain
Assigning power domain to the DMIC interface.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-11-30 17:46:17 -05:00
Tomasz Leman 4dc4327f19 dts: xtensa: intel: fix typo in domain name
Fixing typo in HUB-HP domain name in dts.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-11-30 17:46:17 -05:00
Adrian Bonislawski a45caf868f drivers: dai: add Intel HDA dai
add Intel HDA DAI driver
Long device list in dtsi needs to be refactored in the future

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-11-29 19:42:33 -05:00
Arsen Eloglian 14adcc52db dts: add clkctl definition
Add clkctl definition for Intel ACE

Signed-off-by: Arsen Eloglian <ArsenX.Eloglian@intel.com>
2022-11-28 17:45:20 -05:00
Adrian Warecki 1c5f924628 ace: cavs: dts: Add d-cache and i-cache line size
Added i-cache-line-size and d-cache-line-size values
to device tree for cavs and ace platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2022-11-23 15:39:05 -05:00
Adrian Warecki a8dd856042 dma: dts: gpdma: Add controller attributes to DT
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2022-11-23 15:36:31 -05:00
Adrian Warecki 17916833d3 dma: dts: hda: Add controller attributes to DT
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2022-11-23 15:36:31 -05:00
Adrian Warecki aac03280ec dma: dts: Rename of the dma_buf_alignment to dma-buf-addr-alignment
Renamed the dma-buf-alignment field to a more explicit
and descriptive name dma-buf-addr-alignment.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2022-11-23 15:36:31 -05:00
Arsen Eloglian c67666ae1b board: rename dtsi node 'lps' to 'dfpmcch'
dfpmcch covers lps memory mapping.
Making lps a part of dfpmcch.

Signed-off-by: Arsen Eloglian <ArsenX.Eloglian@intel.com>
2022-11-22 20:03:06 -05:00
Arsen Eloglian 692189d3b5 dts: add dfpmcch & dfpmccu definition
Adding DfPMCCH & DfPMCCU block register definitions.

Signed-off-by: Arsen Eloglian <ArsenX.Eloglian@intel.com>
2022-11-22 20:03:06 -05:00
Kumar Gala a1d0120d91 intel_adsp: Sort SoC nodes by address
Sort SoC nodes by address to make it easier to find them.  As part
of this also move the intel-sha node under SoC where it belongs.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-11-10 22:09:14 -05:00
Adrian Bonislawski 728e387aa2 dts: xtensa: intel: fix alh instances
"alh0: alh1:" will create only one instance and this needs to be
reverted to original form with two instances

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-11-09 09:09:20 -06:00
Kumar Gala bf5afbf823 intel_adsp: Move power domains under lps node for now
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-11-09 06:39:58 -05:00
Jaska Uimonen dd1c88d548 dts: xtensa: intel: fix alh base addr for cavs25
Cavs25 alh definition is currently the same as in ace platform, which is
wrong, thus fix it.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-11-03 10:23:49 +01:00
Flavio Ceolin d486bd1033 intel: ace15: Add adsp-sha entry in DT
Add a DT entry for intel-adsp-sha device in ace15 dts.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-10-31 12:45:33 -07:00
Anas Nashif 52297422fc timer: intel_adsp: use DTS for hardware information
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif f33fb23810 intel_adsp: mem_window: do not depend on instance numbering from DT
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.

For initialization, use bbzero.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 08:28:25 -04:00
Anas Nashif d148ea1d7f intel_adsp: mem_window: support read-only flag
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 08:28:25 -04:00
Anas Nashif d038eb5dc7 intel_adsp: move memory windows to DTS proper
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.

Move FW status to own workflow and separate from window setup.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 08:28:25 -04:00
Adrian Bonislawski 147d9cb127 dts: ace15: add Intel ALH to device tree
Add Intel ALH device tree entries to ace15

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-10-10 21:03:40 -04:00
Jaska Uimonen c9bf8ee4eb dts: xtensa: intel: add dmic dts definitions
Add Intel dmic dai dts definitions for ace15, cavs15 and cavs25
platforms.

Add also pre dts cmake files as the dmic nodes use same address and emit
warnings otherwise.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-10-05 12:41:45 +02:00
Martí Bolívar 55f4075f92 dts: intel: cavs25: hack around awkward DT representation
Apparently, downstream drivers are allocating devices using
DT_NODELABEL(alh0) and DT_NODELABEL(alh1) on a node with compatible
intel,alh-dai. These represent something like "channels" within the
device.

This is a strange choice. It would be better to do something like have
a property with the count of "channels", or one child node per
channel.

It is also a dtc error to have duplicate node names like this, and
will be an error in Zephyr's dtlib soon.

For now, work around this representation issue by replacing it with
something equivalent that doesn't have duplicate nodes. The
representation should be addressed at some point, but not by me.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-09-21 07:55:40 -07:00
Lauren Murphy 85445474f2 boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Lauren Murphy 1983a4c50c boards, dts: fix namespace for intel adsp cavs, ace
Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Ederson de Souza fcdc9c78e2 soc/xtensa/intel_adsp: Get register address from DTS
Instead of hardcoding it where it's used.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza 03a947850d drivers/mm: Get some bit configurations from DTS instead of SoC version
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Andrey Borisovich c75e6cfcb9 soc: intel_adsp_ace1x: Added IPC/IDC implementation
Added IPC and IDC implementation for Intel ADSP ACE1X SoCs.

Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-06 15:33:24 -04:00
Piotr Kmiecik 0acd68247f drivers: ace_v1x wallclock driver
Wallclock driver with functionality required by ACE v1x base firmware.

Signed-off-by: Piotr Kmiecik <piotrx.kmiecik@intel.com>
2022-09-06 17:44:03 +02:00
Andrey Borisovich 2e04bfdfe0 soc: intel_adsp: Refactored IPC/IDC
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.

Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
   - "cavs_host_ipc" node labels to "adsp_ipc" labels.
   - compatible "intel,cavs-host-ipc" renamed to
     "intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
   compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
   - "idc" node labels to "adsp_idc" labels.
   - compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
   so it is suitable for both CAVS and ACE SoC family.
   Moved it from ipm bindings to ipc bindings where it belongs.

Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
   INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
   status of the "adsp-ipc" and "adsp-ipc" node.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-02 08:18:32 -04:00
Tomasz Leman 50452e6ad0 intel: adsp: enable d0i3 in device tree
This patch adds D0i3 definition to available core power states in device
tree.

Additionally, changing the name of the OFF state to better reflect what
is in the documentation.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-09-02 10:53:52 +00:00
Kumar Gala fab8d25fd3 drivers: mm: Add dts binding specific for ADSP Meteor Lake TLB
Add a specific compatiable and binding for intel,adsp-mtl-tlb.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-31 11:17:37 -05:00
Tom Burdick efc0928570 dma/hda: Use the correct register block size for each IP block
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-08-18 14:54:57 -05:00
Krzysztof Frydryk 8dd57467cc drivers: dai: Enable Zephyr runtime power mgmt in Intel SSP driver
Enable Zephyr device runtime power management mechanisms in Intel SSP
driver. This allows Zephyr to track usage reference for power
domain gating.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Krzysztof Frydryk 078de4e021 power_domain: Intel ADSP: Add power gating mechanism for Intel ADSP devices
This adds power domain gating mechanisms for Intel ADSP devices.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Krzysztof Frydryk cbeebe5db6 dts: ace1x: Add lps address
Add lps address to ace 1.x devicetree.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Anas Nashif 6e57a57c53 intel_adsp: ace: reduce hda dma channels
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-28 15:48:00 -04:00
Ederson de Souza 49d1583e2a soc/xtensa/intel_adsp: Enable WOVCRO based on platform support
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-07-28 11:04:05 -04:00
Kumar Gala 136960e071 dts: xtensa: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 12:57:35 -05:00
Tom Burdick c225cf3b8a dma: HDA rename prefix from cAVS to ADSP
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-14 17:53:46 +00:00
Tom Burdick 3824024f77 dma: hda link driver fixups
Fixes configured DMA direction for HDA link in/out drivers.

Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-13 10:55:17 -04:00