This patch adds support for PWM blink which is found in intel's
PCH hardwares.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Changes the Kconfig option to allow disabling mutex support, this
is to allow other Kconfig options to disable the feature.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Change the default mbox initialization priority so that it initializes
before ipc, as some ipc drivers depends on it.
Found with:
$ west build -p -b nrf5340dk_nrf5340_cpuapp \
samples/subsys/ipc/ipc_service/icmsg_me \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /ipc/ipc1 POST_KERNEL 46 <
/soc/peripheral@50000000/mbox@2a000 POST_KERNEL 50
ERROR: /ipc/ipc0 POST_KERNEL 46 <
/soc/peripheral@50000000/mbox@2a000 POST_KERNEL 50
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The underlying HAL driver may improperly forward an samplerdy event even
if it's disabled in the configuration. Ignore the event to prevent error
logs until the issue is fixed in HAL.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
remove the sdk based TOTAL_DMA_CHANNELS macro and instead just use the
zephyr driver's num_of_channels field
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
When reading multiple ADC channel in parallel, an ADC command chain will be
build. This is similar to a linked list, as every command references the
next command.
Before this patch every ADC command after the first, would always reference
this initial command. So that during execution only two commands (the last
and first) would be executed which resulted in readout of only two analog
values. As Zephyr expected more to come in, the `read_adc` function would
block endlessly.
The patch fixes the behaviour and allows a correct chain to build up.
Signed-off-by: Elisabeth Friedrich <auxsys@flowerpot.me>
PCIe devices refer to interrupt nodes, but are initialized with the same
priority, making the sequence depending on the linking order. Add a new
symbol and set it to one unit after intc to ensure that the
initialization sequence is stable.
Found with:
west build -p -b qemu_cortex_a53 \
samples/drivers/virtualization/ivshmem/doorbell \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /soc/pcie@4010000000 PRE_KERNEL_1 40 <
/soc/interrupt-controller@8000000/its@8080000 POST_KERNEL 40
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The intc_gicv3_its driver is currently initializing in POST_KERNEL, but
PCIe device nodes depends on it and are initialized earlier. Change the
init level to PRE_KERNEL_1 to sort that out, and also put the driver in
line with other interrupt controller drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The eSPI, I2C, and SPI emulators use devicetree macros to build an array
of devices on the virtual bus. Currently, they will add device nodes that
are not status-okay. This leads to linker errors because the respective
device drivers would not have instantiated device structs for these
nodes --assuming the driver was even compiled. This can be frustrating
if nodes need to be disabled for debugging or configuration purposes.
Update the bus emulators to only consider status-okay nodes by changing
the macros used to iterate over bus devices.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Removed the unneccessary casts in the functions to remove warnings
during build for SoCs using RAT. Functionality reamins the same,
tested on board.
Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the callback functions of buf_write_received and buf_read_requested
to support buffer mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix for bug:
https://github.com/zephyrproject-rtos/zephyr/issues/59575
The dma version of the version of the driver can
invoke multiple intermediate dma transfers, like
when the spi_buf_set count is greater than one.
However, there is a bug where chip select is not kept
asserted for all intermediate dma transfers required
to process the entire spi_buf_set.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Decouple interface and Wi-Fi APIs, Wi-Fi APIs are common independent of
Wi-Fi offload or implemented natively (This is preparation for
introducing Native Wi-Fi).
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
In order for TCA954X driver to work well, we know that
mux root must be initialized before channels.
(see #37786).
This commit is:
- Ensuring that this condition is met at build.
- Document needed values for menuconfig to help user.
- Edit these values for TCA954X test sample
Fixes#40833
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add MMIO mapping for Renesas CPG driver in order to avoid
mappings inside mmu_regions.c file. Remove MMU region for
Renesas CPG driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Delete IRQ lock/unlock calls from 'rcar_cpg_mstp_clock_endisable',
because 'rcar_cpg_mstp_clock_endisable' function is always called
under spin lock.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associative tables for core and mod clocks.
Add possibility to enable/disable any of core clocks which presents
in the associative table.
Add handler for setting rate to driver and use generic rcar cpg
function for getting rate.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associated tables of clocks and API for working with these tables,
from this moment the relationship between clocks and their divider are
built. After set rate of some Core clock, driver has to update all
in/out rates of all childrens recursively. During get/set rate calls
if out rate is unknown, we try to get parent in/out rates and its
divider, in case when parent doesn't have valid in/out rates we get
parent of parent and so on until we get parent with a valid in or out
rates.
Add generic Renesas functions for get/set rate of CPG.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Move cpg log module declare to common rcar cpg file. If the module
consists of multiple files, then LOG_MODULE_REGISTER should appear
in exactly one of them. Each other file should use LOG_MODULE_DECLARE
to declare its membership in the module.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add MMIO mapping for PFC Renesas driver in order to avoid
mappings inside mmu_regions.c file.
Add a new system init function pfc_rcar_driver_init to PFC
Renesas driver for invoking a memory mapping macro.
Note: PFC Renesas driver doesn't use Zephyr Device Model.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add MMIO mapping for UART Renesas driver in order to avoid
mappings inside mmu_regions.c file(s).
There are a lot of changes inside SCIF driver inside this
commit, because reg addr and size may be stored in RAM or
ROM and appropriately in different driver structures data
or cfg, and, because the name of field reg base is changed.
Note: it is common approach according to Zephyr documentation.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Added Region based Address Translation (RAT) module driver. Required by
a few Texas Instruments SoCs to fucntion. Uses
sys_mm_drv_page_phys_get() API with device_map() for address translation.
Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
The block data length field should be in bytes. Setting this to a value
that is not a multiple of the data size results in a user setting error.
Running the ADC DMA test prior to this commit:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/adc/adc_dma
E: Transfer Error.
I: tc: 0, ht: 0, dte: 0, ule: 0, use: 1
E: DMA sampling complete, but DMA reported error -5
Existing tests using DMA on the nucleo_u575zi_q were not effected
because they only use a data size of one and continue to function
as expected:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/spi/spi_loopback \
-DOVERLAY_CONFIG="overlay-stm32-spi-dma.conf"
SUITE PASS - 100.00% [spi_loopback]: pass = 1, fail = 0, ...
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/dma/loop_transfer
SUITE PASS - 100.00% [dma_m2m_loop]: pass = 3, fail = 0, ...
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
The tables for the dest and src data width constants were incorrectly
swapped. This commit uses the correct constants and renames the tables.
This change is only cosmetic for the stm32u5 since these constants are
the same but the existing names were probably inherited from another
driver where the p_*/m_* prefix was more appropriate.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
Enable DMA error interrupts so that transfer errors are logged and
reported to the callback.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Avoid integer overflow in temp_sq calculation.
For an analysis of the value ranges for the temp_sq calculation
of mx5837-02 see below:
calculation:
dT = adc_temperature - ((int32_t)(data->t_ref) << 8);
data->temperature = 2000 + (dT * data->tempsens) / (1ll << 23);
temp_sq = (data->temperature - 2000) * (data->temperature - 2000);
given needed storage sizes:
t_ref is uint16_t,
adc_temperature is uint24_t,
data->tempsens is uint16_t,
ranges
=> dT: -16776960 <= dT <= 16777215 (25 bit)
=> data->temperature (TEMP):
intermed.(mult): -1099478073600 <= x <= 1099494785025 (41 bit)
TEMP: 2.000 - 131068 <= TEMP <= 2.000 + 131.069
TEMP: -129068 <= TEMP <= 133069 (17 bit)
So worst case we need 17 bit for TEMP, so the square of it would
overflow an int32_t. The nominal measurement range is
only -40 to 85°C, meaning a range of -4000 to 8500.
So normally the result for temp_seq would fit into a int32_t,
but we cast to be better safe than sorry. Also the 64-bit
multiplication won't be the dominating operation of the
whole calculation.
Fixes#58585
Coverity-CID: 316294
Fixes#58594
Coverity-CID: 316521
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the RCR_PRMS field to toggle the promiscuous mode in the Ethernet
controller.
Register a set_config function that can make use of the field when
CONFIG_NET_PROMISCUOUS_MODE is enabled.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Replace the timeout for a SPI transceive in slave mode for STM32 DMA
operations with a K_FOREVER. Being an SPI slave means we do not
know when the transaction will start, hence it does not make sense
to have a timeout in such a case.
This will resolve issue #60000.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The adc_driver_api structure provides .ref_internal
which previously was unset.
Now .ref_internal is set to the proper value.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Move LOG_DBG print just after the printed h/w register is read, to avoid
coverity complaining about uninitialized variable.
Fix:
Coverity-CID: 316407 (issue #58591)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Split the native ptty serial driver in a top and bottom
to enable using it with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Refactor the part of the flash simulator that interacts with the
host when build for native platforms, so it is possible to use
it also with the embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix `PWM_SetupPwm` function being called with `numOfChnls`
argument equal to 2, when in fact only one channel is being set up.
Also add 'U' suffix to `pwmFreq_Hz` unsigned integer argument in
the function call.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
In case of remapped reference counter for physical page
is differ to zero, but TLB entry for virtual address equal to
physical address will be disabled. Valid entry will be somewhere
in virtual space where particular physical page is remapped.
Since in adsp_mm_save_context() routine we go through physical
memory range, we need to include these pages in context save loop.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Currently MIPI devices are set to initialize before display drivers,
which is incoherent with how the mcux mipi-dsi device is declared in the
device tree.
This is detected with build time priority checking:
west build -p -b mimxrt595_evk_cm33 samples/drivers/display \
-DCONFIG_CHECK_INIT_PRIORITIES=y
ERROR: /soc/peripheral@50000000/mipi_dsi@31000 POST_KERNEL 40 <
/soc/peripheral@50000000/lcdif@210000 POST_KERNEL 85
Note that this also changes the priority of dsi_stm32, though that
should be ok since does not appear to have other dependencies in
devicetree.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Boot level based on parent node (PCI or no PCI device). Some platforms the
PCI bus driver depends on ACPI sub system to retrieve platform information
such as interrupt routing information. But ACPI sub system currently
support only post kernel and hence such platforms the UART driver instance
init should be invoked only post kernel in case parent node is PCI.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.
This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):
rtc: rtc@... {
compatible = "ti,cc13xx-cc26xx-rtc";
...
timer {
compatible = "ti,cc13xx-cc26xx-rtc-timer";
...
};
counter {
compatible = "ti,cc13xx-cc26xx-rtc-counter";
...
};
pps {
compatible = "ti,cc13xx-cc26xx-rtc-pps";
...
};
};
Or alternatively an MFD pattern with similar requirements.
Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.
Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Refactor the host libC accesses to use the native simulator
host trampolines.
In this way we support building this driver with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The stm32 UART can output a "driver enable" signal on the RTS pin that
allows controlling e.g. external RS-485 drivers.
This can already be configured through the devicetree using the `de-*`
properties, but not through uart_configure(). This commit enables the use
of .flow_ctrl=UART_CFG_FLOW_CTRL_RS485.
This is supported on all devices other than l1, f1, f2, and f4 as found by
this search:
$ grep -rLw USART_CR3_DEM ../modules/hal/stm32/stm32cube/*/soc/*.h |\
grep -vE 'system_|partition_|stm32[^0-9]+[0-9]?xx\.h' |\
cut -d/ -f6 |\
sort -u
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The code declares variables in switch-case blocks. This
seems to compile without an error on GCC 11 and newer,
but older compilers don't accept this code.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
The ISM330DHCX driver immediately segfaults when run in SPI mode. A bad
pointer is being passed into the `dev` param of `ism330dhcx_spi_read`.
Tracing this back, it appears that the handle field of the ctx struct
is being set to the device's data struct while `ism330dhcx_spi_read`
expects `ctx->handle` to be a pointer to a device struct.
Modify `ism330dhcx_spi_init()` to insert the correct pointer into the
context struct. Unfortunately this requires a cast to discard the
`const` qualifier, but this is how it is done in I2C mode (see
`ism330dhcx_i2c_init()`). The only other way would be to change the
declaration of `stmdev_ctx_t`, which is owned by the HAL module.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
gpio_nrfx_port_get_direction() is meant to check which inputs
are enabled, and does so by checking one bit at a time
and setting that bit into the "input" parameter.
But "input" was never zeroed, so any garbage ones it
may have remains.
Zero it.
This fixes a problem where if the "input" parameter was not
zeroed by the caller, the result of the funcion call
is undefined.
Detected by valgrind on:
tests/drivers/gpio/gpio_get_direction
Conditional jump or move depends on uninitialised value(s)
by gpio_get_direction_test_disconnect (main.c:64)
Conditional jump or move depends on uninitialised value(s)
by gpio_get_direction_test_output (main.c:102)
When running this test for the nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Static code analysis it has highlighted that a variable is beeing
accessed before initializing. This is a very minor fix
to resolve this potential issue.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
This change corrects the it82xx2 resumed/suspended mechanism and power
policy flow. The sof package is used to judge if the device can be set as
suspended state. If there is no sof package received(suspended), the chip
power policy is set as standby(deep doze) mode. Meanwhile, the USB D+
interrupt is enabled. The interrupt is triggered at resume signal(from J
to K state). Chip sets its power state as active(doze) mode and disable
the interrupt.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add SHA256 accelerator support for it8xxx2 series.
This driver passes the following test:
tests/crypto/crypto_hash/
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Since we have state that gets mutated between tests in the SBS fuel gauge
emulator we ought to reset its state before each test.
Add a reset rule to the SBS fuel gauge emulator that resets the state
before each test. Note: This includes allowing the emulator state to be
modified by user-threads.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
In order to support easier setup of test scenarios with fuel gauge
emulators, we should expose an API that can change internal emulator state.
Add a minimal fuel gauge emulator backend API for setting the charging
current and voltage with a sample implementation in the emul_sbs_gauge with
an associated driver test.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Calculate the calibration value at compile for ina23x.
Maximizes the precision of the calcualtion value by
using 64bit math at compile, allows for removal
of rshunt config option.
Code cleaned up with clang-format.
Co-authored-by: Trent Piepho <tpiepho@gmail.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Changes rshunt-milliohms to rshunt-micro-ohms allowing for current
sensing of greater than 16.4A (1mOhm resistor). This is commonly
set to 100 uOhm for VMU/FMU boards/applications.
Co-authored-by: James Goppert <james.goppert@gmail.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
The `SPI_EMUL_INIT(n)` macro used to instantiate SPI bus emulators
builds an array of SPI devices attached to the bus, but always checks
instance #0 of the bus and not `n`. This makes multiple instances of an
emulated SPI bus unusable and popualtes them all with bus 0's devices.
Change the `0` to `n`, which matches how the I2C bus emulator does it.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Update ESP AT modem driver to control the network interface dormant
state based on the network connection status, as described in the docs.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
SIUL2 may require multiple interrupt handlers instead of a single one as
currently supported for S32Z/E. This is needed to enable support on
S32K3.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Support pin control for NXP S32K3 devices and enable it by default on
mr_canhubk3 board configuration.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The clock controller is a singleton controller for all the system-level
clocks (XOSC, PLL, CGM, etc) to provide run-time information to the
peripheral device drivers about the module's clocks.
Clock configuration is not yet supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Split the SDL GPIO emulator driver in a top and bottom
to enable using it with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Split the SDL input driver in a top and bottom
to enable using it with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Split the SDL display driver in a top and bottom
to enable using it with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Merges the condition for `UART_INTERRUPT_DRIVEN || UART_ASYNC_API` into
`UART_MCUX_FLEXCOMM_ISR_SUPPORT`.
Signed-off-by: Alp Sayin <alpsayin@gmail.com>
When UART_INTERRUPT_DRIVEN=n, mcux_flexcomm_isr and the data structure
inside is left unused. This patch turns off the build of the entire ISR.
Signed-off-by: Alp Sayin <alpsayin@gmail.com>
without the call of LPUART_ClearStatusFlags(), the interrupt can
immediately trigger again, blocking the application.
CONFIG_ASSERTS=n removes the assert() including the call of
LPUART_ClearStatusFlags().
Also removed LPUART_ClearStatusFlags call for unclearable
kLPUART_TransmissionCompleteFlag.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Since clocks aren't declared in the devicetree for the stm32mp1
co-processor. Read the resulting clock divider here instead.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Since clocks aren't declared in the devicetree for the stm32mp1
co-processor. Read the resulting clock divider here instead.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Add a small delay between reading the transport header and reading the
HCI data. Failing to do so on a nRF9160<->nRF52832 link was reliably
resulting in the nRF9160 trying to read data before the nRF52832 had
set up the SPI transaction, resulting in the host reading a buffer full
of 0x00 and having to run the entire read result again.
Transceiving a 10 byte packet takes at least 31uS, while 100 byte
packets are around 150uS (duration of `spi_transceive` call). Waiting
1 tick to eliminate the need for most retransmissions is a valid
tradeoff.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add an option that signifies that the ESP modem may be reset at the same
time as the SoC by an external source. When this is the case, we first
wait for an unsolicited "ready" message from the modem, before
attempting to reset the device. This prevents two initialisation
sequences attempting to run at the same time.
We still want to wait for the complete initialisation sequence to
complete before returning in this case.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Don't unconditionally set the carrier to the off state in
`esp_iface_init`, as this is already done in `esp_reset` and the
function may be called after the modem has already completed the init
sequence and called `net_if_carrier_on`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Wait for the init process to finish again, previously removed in
a8e6fc0b83. The original reasoning (deadlock with net interface locking)
no longer applies now that `esp_reset` is called in the device init
function, not in `esp_iface_init` (332a6f084a).
Without this change, if `reset-gpios` or `power-gpios` is set,
`device_is_ready` will return true even if the chip has fallen off the
board, as no communication is validated with the board.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Support device power management in spi_nor driver. Only use
SUSPEND/RESUME if `CONFIG_SPI_NOR_IDLE_IN_DPD` is not enabled to avoid
state conflicts.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Quite a few of the drivers meant for the POSIX arch
interacted with the host directly, and will not
work when we use an embedded libC.
Until we fix them, let's add the appropriate
kconfig dependencies to avoid users trying to build them.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Enable automatic temperature measurements during charging.
Allows the PMIC to charge when the host is in low power mode.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
The vbus current limit is now written to the vbus startup
register. It is now applied at all times and does not need
to be updated on charger insertion.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Because they are needed in SoC power.c, clock control init functions
for all other STM32 series has been exported as global.
This commit exports stm32_clock_control_init function as global for
STM32H7 series as well, making custom power management
implementations for STM32H7 series possible.
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
NO_CACHE cannot be selected for certain cores.
Use ARCH_HAS_NOCACHE_MEMORY_SUPPORT as the condtion
to select NO_CACHE config
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The blink command should blink until the user presses a key, however on
some systems a pending keypress is present when entering the loop
causing it to immediate exit before getting a chance to blink.
Add a dummy read to clear the buffer before starting the blink loop.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
The device passed to the DMA callback is the DMA device. Instead use
the ADC device available in the private data.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
Add fixed-clock clock control driver. This is a first step towards
making fixed-clocks a first-class citizen in the clock control
framework.
Since the change is hidden behind a Kconfig enable this is opt-in
for now.
Signed-off-by: Moritz Fischer <moritzf@google.com>
