Commit graph

70 commits

Author SHA1 Message Date
Laurentiu Mihalcea 57ca49aaa9 soc: arm64: nxp: mimx9: Create identity mappings for regions in SOF dts
This commit creates identity mappings for all memory regions required
by SOF. This is needed because drivers using these memory regions have
not yet been ported to Zephyr.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-04-19 10:01:19 +02:00
Laurentiu Mihalcea e1841a966d soc: arm64: nxp: mimx9: Modify linker script to include SOF sections
Since SOF uses some extra sections we need to add them to the linker
script. The used linker script is simply a copy of arm64 linker script
with SOF regions included. This is because conditionally adding sections
to the main arm64 linker script is not really desirable.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-04-19 10:01:19 +02:00
Gerard Marull-Paretas a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Rodrigo Cataldo a25996a661 soc: arm64: qemu: bump highest IRQ when ITS is enabled
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2023-04-07 13:26:01 +02:00
Luca Fancellu 0deeb5ff65 soc: include: fvp_aemv8r: Define device memory as device tree node
A recent change introduced the possibility to declare MPU memory
regions using the device tree and the framework described in
zephyr/linker/devicetree_regions.h.

So remove the device region declared in mpu_regions[] and the used
defines for the addresses, rename REGION_DEVICE_ATTR to REGION_IO_ATTR
in arm_mpu.h to be compatible with the framework and add a device tree
node to fvp_baser_aemv8r.dts to describe the device memory region.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
2023-03-27 13:20:47 +00:00
Yanqin Wei a1f55c63b3 soc: fvp_aemv8r: add mpu region from device tree
Some platforms need to define multiple memory regions with
various attribute. This patch adds dts defined regions in the mpu
configuration. The memory attribute can be set in the device tree.

Signed-off-by: Yanqin Wei <Yanqin.Wei@arm.com>
2023-03-20 09:54:35 +01:00
Grant Ramsay 76a4b44227 soc: arm64: ti_sitara: Add pinctrl support for TI AM6X A53 SoC
TI Sitara processors use the K3 architecture

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-03-02 13:50:06 +01:00
Grant Ramsay f92dd6d357 drivers: serial: Name the NS16550 variant Kconfig choice
Naming this choice allows setting a default value in defconfig.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Grant Ramsay 84f92c7bc3 soc: arm64: Add TI AM6234 SoC A53 support
Add minimal SoC support for the TI AM6X series Cortex-A53 Core.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Jiafei Pan 921b32663b board: arm64: add pinctrl support for imx93 evk board
1. Added imx93-pinctrl dts binding yaml
2. Added imx93 pinctrl_soc.h header file
3. Updated imx93 dts to enable pinctrl for lpuart.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-12-20 09:22:40 +01:00
Jiafei Pan 08978d146c soc: arm64: add i.MX93 MPU support
Add i.MX93 Cortex-A Core support on Zephyr.

i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-12-20 09:22:40 +01:00
Henri Xavier 5de23dab59 boards/arm64: Add QEMU Virt KVM support
Zephyr already has an AArch64 QEMU Virt TCG board.
We add a KVM version of it.

Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-11-17 11:16:08 +01:00
Huifeng Zhang 52cdf2aaf3 boards: fvp_baser_aemv8r: remove SOC_FVP_AEMV8R_EL2_INIT code
Now that VMPIDR_EL2 will be initialized in z_arm64_el2_init, the code
that I wrote for initializing VMPIDR_EL2 on fvp_baser_aemv8r can be
removed.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2022-10-12 18:46:49 +09:00
Henri Xavier a43b37bb07 boards: Add support for Khadas Edge-V board
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.

Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-10-08 18:32:14 +02:00
Jiafei Pan 97fe92d481 boards: arm64: add imx8mn board support
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.

Zephyr OS is ported to run on the Cortex®-A53 core.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-09-05 10:17:13 +02:00
Jiafei Pan 8b92141878 boards: arm64: imx8mm/p: unify soc name
Replace imx8mm/p with mimx8m/p to unify name with the
other software components.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-09-05 10:17:13 +02:00
Jiafei Pan 93d59266b4 soc: arm64: imx8mm/p: enable pinctrl for soc and boards
Enable pinctrl on imx8mm and imx8mp platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-09-05 10:17:13 +02:00
Jiafei Pan 3b722abf8f boards: arm64: imx8mm/p: unify soc name in configuration item
Used unified name "IMX8M*" to replace "MIMX8M*".

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-09-05 10:17:13 +02:00
Jiafei Pan 234c91d62f soc: arm64: imx8mm/p: update SoC part number and name
To be synced with drivers in hal_nxp.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-09-05 10:17:13 +02:00
Boon Khai Ng ef3c0d2fa3 soc: arm64: intel_socfpga: Increase kernel VM size and memory size
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
2022-09-01 14:30:59 -04:00
Henri Xavier 3ba0cb19ea soc/arm64: Do not allow userspace to directly access peripherals
In some arm64 boards, MMU regions are set so userspace can access all
peripherals (MT_P_RW_U_RW), including the GIC.
This seems like a mistake, which has been copy/pasted in some boards.

Change this to no userspace access by default (MT_P_RW_U_NA),
like the other boards.

Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-08-05 06:28:57 +01:00
Kumar Gala 5b9e0b615c clock_control: remove Kconfig.defconfig setting of clk control drivers
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control.  Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-29 14:12:12 +02:00
Dmytro Firsov f4cea5da70 xenvm: drivers: xen: add Xen grant table driver
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2022-06-28 22:34:26 -04:00
Luca Fancellu 25142045b7 soc: qemu_cortex_a53: remove pl011 entry from mmu_regions array
pl011 driver uses the new device model and maps the mmio space,
so there is no need anymore to add the entry to the mmu_region
array.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
2022-06-07 11:54:13 +02:00
Luca Fancellu 5f103648c6 soc: fvp_aemv8a: remove pl011 entry from mmu_regions array
pl011 driver uses the new device model and maps the mmio space,
so there is no need anymore to add the entry to the mmu_region
array.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
2022-06-07 11:54:13 +02:00
Gerard Marull-Paretas 5b55440c08 soc: arm64: xenvm: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 41e47fbf53 soc: arm64: qemu_cortex_a53: remove unused definition
SZ_1K was never used.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 22dfbca6f0 soc: arm64: qemu_cortex_a53: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 5806d3bffa soc: arm64: nxp_layerscape: remove redundant soc.c source
The soc.c source file did nothing, so just remove it. Remove soc
directory from the include list as well, since there's no header in the
directory that needs to be exposed to the Zephyr build.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 833e6490f9 soc: arm64: nxp_layerscape: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas ebd5c8d46d soc: arm64: nxp_imx: remove dummy C file
A dummy C file was present in the imx8m SoC directory for no reason,
delete it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 27ec244130 soc: arm64: nxp_imx: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas e2830c7a0a soc: arm64: intel_socfpga: delete redundant soc.h
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Note that in this case, none of the definitions are used in-tree.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas e74c083814 soc: arm64: intel_socfpga: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

In this case, the file did not use anything defined in <soc.h>, it only
required access to integer types, e.g. uint32_t.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 0573edb47f soc: arm64: intel_socfpga: remove dependency on soc.h
SOCFPGA_SYSMGR_REG_BASE is the only definition from soc.h used in tree,
move it to the file using it. Note that this looks suspicious: base
address should come from Devicetree. This patch will allow to drop
soc.h.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas e78c23c2da soc: arm64: intel_socfpga: improve soc.h includes
arch/cpu.h was not needed, devicetree.h and sys/util.h are required for
DT API and ARRAY_SIZE().

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 69f9a55f4f soc: arm64: fvp_aemv8r: improve include list
Make source self-contained by including what is needed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas cb9120b7cd soc: arm64: fvp_aemv8r: remove empty soc.h
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 854ec6cf16 soc: arm64: fvp_aemv8a: fix soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas f0e9284097 soc: arm64: bcm_vk: viper: remove redundant soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas 9945dd5e52 soc: arm64: bcm_vk: viper: improve soc.h include list
The header only required util_macro.h for BIT().

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Daniel DeGrasse 946b9dc1e1 boards: imx8mm: add partial pin control support
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Eugene Cohen 816229128d arch/arm64: update gicv3 sre enablement
Fix writing of ICC_SRE_EL3 to or-in bits to align
with original intent to read-modify-write this
register.

Also disable FIQ and IRQ bypass so interrupt delivery
occurs through GIC.  Platforms may choose to override
this behavior in z_arm64_el3_plat_init implementations.

Remove ICC_SRE_EL3 config from viper and qemu since
this is now handled in the arm64 arch core.

Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
2022-05-10 09:13:20 +02:00
Gerard Marull-Paretas d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas 0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Gerard Marull-Paretas c925b5991a include: remove unnecessary autoconf.h includes
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-05 11:18:20 +02:00
Peng Fan 01002a3c8d nxp: imx: support i.MX8MP EVK board
Support i.MX8MP EVK A53 with/without jailhouse hypervisor
 - Add dts/dtsi
 - Add board file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan 9be846bf46 soc: arm64: imx8m: share the dummy file
Move the file from board to soc to make it could be shared by
i.MX8M family. When MCUX_HAL supported in future, this file could
be dropped.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan b63c363989 arm64: nxp_imx: drop a53 linker file
We could reuse the common linker script, no need use i.MX8M specific
one. BTW i.MX8M family is based on A53 core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan 84081ffddc soc: arm64: nxp_imx: Add i.MX8M Mini SoC A53 support
Add minimal SoC support for the NXP i.MX8M Mini series Cortex-A53 Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-09 09:56:12 -06:00