Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level
Fixes: #57655
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
(resubmitting after it has been reverted by 0f2a352cbd ('Revert
"xtensa: remove ELF section address rewriting"')
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The Mi-V implements the A extension therefore it shouldn't use the C
version. The built-in version generates code with proper machine
opcodes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Rename soc to mimx8ml8 to link this board to the
MIMX8ML8 device from nxp_hal/mcux/mcux-sdk/.
We need this in order to use the drivers from mcux-sdk.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Do not use XTENSA_HAL when building with xt-clang, instead use the HAL
that is provided by the toolchain, similarly to xt-xcc.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Build of Intel cAVS2.5 platforms fails due to undefined reference
sys_cache_data_flush_and_invd_all(). Fix this by adding missing
header include to bring in the inline definition for this function.
Fixes: 6388f5f106 ("xtensa: use sys_cache API instead of custom interfaces")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Move additional cache code related to architecture support into arch.h
and leave cache.h with cache API implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Disable the hardware I2C target detection on the IT82xx2 SoC family.
Note: The register setting of I2C target detection is different in
IT81XX2 and IT82XX2 SOC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
