Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
use helper macros from csr.h instead of inline assembly which results
in cleaner and more maintainable code
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds some structs for interrupt stack frames to make it
easier to access individual elements, and ultimately getting
rid of magic array element numbers in the code. Hopefully,
this would aid in debugging where you can view the whole
struct in debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit creates identity mappings for all memory regions required
by SOF. This is needed because drivers using these memory regions have
not yet been ported to Zephyr.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since SOF uses some extra sections we need to add them to the linker
script. The used linker script is simply a copy of arm64 linker script
with SOF regions included. This is because conditionally adding sections
to the main arm64 linker script is not really desirable.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use one common `if SOC_SERIES_NRF52X` instead of `depends on` for
each particular SoC option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 4be102f8e05a9fa12290d8209a8cb38569265478.
Inclusion of `<system_nrf*.>` from `soc.c` files is no longer needed
since `SystemInit()` is not called from those files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The power off sequence in cavs is meant to be used only by custom pm
policy handler thus guard it with proper ifdefs.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
The native_tasks definition was directly in the soc_inf soc.h
header. But soc.h pulls a lot of other headers.
Some of those could cause conflicts, say with application
headers, for users who only wanted the be able to register
native tasks in a module.
Let's refactor the native tasks definitions into their own header
and include that header from soc_inf's soc.h.
In this way users who need only need to register a native tasks
can just include posix_native_tasks.h, and all previous users
see no change.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Initialization part of this anomaly is now handled internally
by the startup code provided by the MDK.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.
To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.
Signed-off-by: scott worley <scott.worley@microchip.com>
This commit introduces power management support for EFR32BG SoCs.
Tested on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added UART instances and changes to enabled
support for PCIe UART instances.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between
__rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure
this region is covered by the MPU background region so that the static
region for nocache is configured correctly.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.
- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:
```
$ sudo sleep 30 &
$ kill $! # sudo propagates the TERM signal and sleep is terminated
$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$ ps xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```
Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.
- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.
`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU
Signed-off-by: Francois Ramu <francois.ramu@st.com>
A recent change introduced the possibility to declare MPU memory
regions using the device tree and the framework described in
zephyr/linker/devicetree_regions.h.
So remove the device region declared in mpu_regions[] and the used
defines for the addresses, rename REGION_DEVICE_ATTR to REGION_IO_ATTR
in arm_mpu.h to be compatible with the framework and add a device tree
node to fvp_baser_aemv8r.dts to describe the device memory region.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Remove the manually created linker section, because it's already
automatically generated for all sram regions in the DTS with the
"zephyr,memory-region" compatibility.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This reverts commit 7a85983ebc.
This commit was merged prematurely and is causing issues on multiple
platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some pico-sdk drivers call a panic function, originally implemented
as part of the Pico's C runtime. This commit adds a Zephyr compatible
implementation of panic, so that those drivers could be compiled with
Zephyr.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
In general, RTC and TIMER driver implements counter API but there
are exception when those peripherals are used in a custom way
(e.g. for system timer or bluetooth). In that case, system must
prevent using counter based on a reserved instance. Previously,
it was managed by Kconfig options but that cannot be maintained
when switching to devicetree configuration of the counter driver.
A new approach removes Kconfig options and instead adds static
asserts in the files which are using direct peripherals. Those
asserts check if given node is not enabled in the device tree.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Some platforms need to define multiple memory regions with
various attribute. This patch adds dts defined regions in the mpu
configuration. The memory attribute can be set in the device tree.
Signed-off-by: Yanqin Wei <Yanqin.Wei@arm.com>
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Adding this condition will limit the minimum residency time to enter
sleep mode. This will fix tests in test\kernel\sleep\usleep.c causing
longer than expected test times due to going into sleep mode with no
time limit.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enabled GPIO support for rpl_crb board by adding
platform GPIO specific definitions.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Use Device Tree bindings to configure clock source/frequency for enabled
UARTs only.
Get rid of UART clock ungating from `soc.c`, as that functionality has
been moved to the clock controller.
Signed-off-by: Artur Rojek <artur@conclusive.pl>
Add functionality for changing the code location
based on the flash chosen node for RT devices.
Remove obsolete Kconfigs that used to be used
to set the code location for RT devices.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Reusing existing code during CPU init at power gating exit.
Additional changes:
- replacing magic value for memctl and atomctl with more readable
definitions,
- using dedicated macros in place of asm inlines.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Allow selecting between direct SMPS and LDO on the startup. This
enables selecting to use SMPS regulators which can save bit of power.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
