Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add Intel dmic dai dts definitions for ace15, cavs15 and cavs25
platforms.
Add also pre dts cmake files as the dmic nodes use same address and emit
warnings otherwise.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Apparently, downstream drivers are allocating devices using
DT_NODELABEL(alh0) and DT_NODELABEL(alh1) on a node with compatible
intel,alh-dai. These represent something like "channels" within the
device.
This is a strange choice. It would be better to do something like have
a property with the count of "channels", or one child node per
channel.
It is also a dtc error to have duplicate node names like this, and
will be an error in Zephyr's dtlib soon.
For now, work around this representation issue by replacing it with
something equivalent that doesn't have duplicate nodes. The
representation should be addressed at some point, but not by me.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This patch adds D0i3 definition to available core power states in device
tree.
Additionally, changing the name of the OFF state to better reflect what
is in the documentation.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This reverts commit fdd47f39be.
After v4.4.1, write-block-size is no longer needed to be 32-bytes
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Enable Zephyr device runtime power management mechanisms in Intel SSP
driver. This allows Zephyr to track usage reference for power
domain gating.
Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Fixes configured DMA direction for HDA link in/out drivers.
Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
- adds properties 'group', 'index' and 'prescaler'.
- updates board's dts to include those properties.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This seems to cause a crash when running tests/boards/intel_adsp/hda and
also causing issues downstream on SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
This commit moves the hardware configuration for ledc
peripheral to the device-tree instead of Kconfig.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Bindings for Intel HDA now require the buffer alignment property to be
set.
Sets the property to 128 bytes for the common Intel cAVS device tree as
was implied by the tests cases.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Current write block size does not guarantee proper
write operation, what might cause corrupted data.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
On Espressif SoCs, the pin controller is a virtual device.
Pin settings are actually controlled in a distributed way.
Therefore, that node does not belong to the SoC bus.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
