Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since d992683db5 (soc: arm: replace redundant config option for
caches for nxp_imx), RT1xxx series will not have cache enabled at boot
unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance,
enable CONFIG_CACHE_MANAGEMENT by default.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.
The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the redundant cache config options for kv5x and use
the sys_cache* functions to enable the caches. This will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache* for enabling the caches in nxp_s32. This automatically
considers CONFIG_CACHE_MANAGEMENT and will activate the
cases only if this is active.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This option is no longer needed, all SoCs have been moved out from
soc/riscv/riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganized as follows:
- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)
Also moved out of riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.
[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
fpga-and-soc-design-tools/mi-v
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganize following the hierarchy found in the vendor website [1]:
- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518
Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].
[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
B91_Generic_Starter_Kit_Hardware_Guide/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When Power Management is enabled (CONFIG_PM=y),
the CONFIG_IDLE_STACK_SIZE of 320 is not enough :
Increase its size to 512.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The defconfig.series file for the stm32f4 incorrectly redefines
the PM Kconfig in order to select two dependencies, COUNTER and
COUNTER_RTC_STM32_SUBSECONDS, instead of setting a default for
them if PM is included.
This commit fixes the error described above.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Currently SOF has disabled CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE option and
use pm_suspend_devices() to suspend and resume IPC device during D3
power flow. The pm_suspend_devices() function skips suspending devices
that are busy. In very rare cases, the IPC device is busy during the
power state transition, which results in the device not being restored
during reboot. This happens when FW sends a message to the HOST and
waits for ACK, and the HOST simultaneously sends a SET_DX message to the
DSP. This suspend/resume logic in IPC driver does not work well when the
system enters the D3 state because it is not a suspend state, but rather
a power-off. IPC does not require suspending, only reinitialization when
exiting D3. We cannot avoid this one missing ACK and it cannot block the
DSP from turning off.
When FW receives a SET_DX message it checks whether it can enter the D3
state and then returns an error (via IPC) or calls the pm_state_force
function. Success response is sent directly from power_down assembly and
not via ipc driver. This is because after receiving the response, the
HOST will turn off the DSP.
In order for the transition to D3 to take place, only the primary core
can be active, all pipes must be stopped (and therefore all modules in
FW). The only active thread at this time is the Idle thread. Driver on
the host will not send another ipc because is still waiting for
response. FW can try to send only two notification:
- FW exception: from this place there is no return to continue the power
transition,
- log buffer status: skipped, they remain in the queue without being
sent.
I'm moving pm_device_busy_clear(dev) from IRQ handler to
intel_adsp_ipc_send_message function so the pending ACK does not block
power transition.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
HDA DMA driver uses an excessive value of 128 bytes as required alignment
for DMA buffer size. This may result in the correct buffer size (e.g.
32-byte aligned, which is DT-compliant) being silently truncated before
writing it into DGBS register. This patch changes the requirement to the
value implied by DGBS register format (effectively reduces to 16 bytes).
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
The previous implementation of the sys_arch_reboot function
for the Atmel SAM series was using NVIC_SystemReset.
This caused a reboot time of around 20 seconds on a SAM4SA16CA,
which is now reduced by directly writing to the
reset controller control register (RSTC_CR).
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
