This file was moved to the `dts/arm64` directory 3 years ago:
3539c2fbb3
However, the original file in `dts/arm` was left by mistake. Since then,
it's been unused and seldom updated, but it hasn't diverged much.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Driver already handles the case when 'reset-gpios' is not provided, so
remove 'required: true' from bindings to allow boards / shields definition
without reset signal being connected to any Zephyr controlled GPIO.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the management
of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This file is basically a copy of the AM62x M4 dtsi but an
additional mcu_uart1 interface.
The internal clock frequency feeded into the UART IP is
96 MHz instead of 48 MHz, which is different to the AM62x.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
We define two frequencies in the am62x_m4.dtsi file.
Use DT_FREQ_M for both frequency to make them more
human-readable and easier to understand.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The commit restricts erase-value to either 0xff or 0x00.
On program-erase type devices writes can only change from
erase value of bit to opposite, ease usually consists of two
operations which is programming the opposite value to every bit
of erase range and then turning back all bits to the "erase-value";
above makes it impossible to have erase value of device to be other
than 0xff or 0x00.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
add gpio_intel driver with acpi based resource enumeration support.
Also updated test cases overlay with new dts entires.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
The ace20 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The ace15 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The tgph description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set RTC clock source to the internal 32 KHz LPO. Currently RTC clock is
used to source RTC counter and FTM counter.
Fixes#71289
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO. To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.
The original PIO source code is also included as a reference.
Corrected 3-wire tx/rx counts.
Enable half-duplex code based on DTS configuration
Replace runtime checks with static BUILD_ASSERT()
Remove too-fussy Kconfig options
Removed PIO source per review request
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The MAC address macros are ridiculous in this driver.
Rewrite to be simpler and use eth.h common function.
Also, clarify the mac address generation on the DT overlays.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds a DAC driver for Texas Instruments DACx0501 family of devices
Signed-off-by: Eran Gal <erang@google.com>
Co-authored-by: Martin Jäger <17674105+martinjaeger@users.noreply.github.com>
Add a VEVIF node to be used for communicating with SysCtrl (cpusys).
This is the only part of the SysCtrl VPR exposed to local domains.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Enable MIPI mode to be set via devicetree, for displays that support
multiple MIPI DBI modes. This commit also adds new helpers for displays
that allow drivers to initialize the entire MIPI DBI configuration
structure from devicetree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates the SRAM configuration in the STM32L475 device tree:
- `sram0` size reduced from 128K to 96K.
- `sram1` added with 32K.
These changes correct memory settings to prevent initialization failures.
Signed-off-by: Tianshuang Ke <qinyun575@gmail.com>
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
If I2C3 switches from GPH1/GPH2 to GPB2/GPB5, extend setting
is required.
Test: Accessing I2C is normal if I2C2, I2C3, I2C5 are switched.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Copy the DMA channel information to both UART and SPI
instances of the Flexcomm as only one of them can be
active.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all devices are initialized at boot time (following their
level and priority order). This patch introduces deferred
initialization: by setting the property `zephyr,deferred-init` on a
device on the devicetree, Zephyr will not initialized the device.
To initialize such devices, one has to call `device_init()`.
Deferred initialization is done by grouping all deferred devices on a
different ELF section. In this way, there's no need to consume more
memory to keep track of deferred devices. When `device_init()` is
called, Zephyr will scan the deferred devices section and call the
initialization function for the matching device. As this scanning is
done only during deferred device initialization, its cost should be
bearable.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
