for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Flash is clocked with HCLK, while CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
reflects SYSCLK. HCLK = SYCLK / AHB prescaler.
When dealing with flash latency, use HCLK instead of SYSCLK.
This changes reverts a abusive change done in an old commit (efd8ee465c)
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Latency should be set before HCLK clock increase. Not doing so can result
in broken behavior.
For instance, at startup, MSI is @4MHz on L4 series.
If MSI is required to be configured at 48 MHz for future use a USB clock,
this will be done in set_up_fixed_clock_sources(). If flash latency is
not correctly set at this point fetching flash will fail..
Move flash latency configuration before setting up fixed clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Based on RM0456, each PLL in the STM32U5 has the
capability to work either in integer or fractional mode.
In this update, the fractional mode can be enabled
by setting the fracn value in the device tree.
Signed-off-by: Jatty Andriean <jandriea@outlook.com>
Add an explicit include of zephyr/arch/cpu.h before fsl_clock.h so that
the Zephyr cpu definitions are parsed before the hal ones.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
According to the reference manual the overdrive should be enabled after
setup of the sysclock (HSE or HSI) and enabling the PLL (PLLON).
The flash latency should be enabled after the PLL has been turned on,
but before switching the system clock to the PLL.
Signed-off-by: Max van Kessel <max_van_kessel@msn.com>
LSI clock configuration for STM32WBA is located in backup domain.
The backup domain needs to be enabled before the LSI can be enabled.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
RCX and RC32K oscillators are not precisely trimmed.
This code allows to measure actual frequency of those two
oscillators.
Device tree binding were extended to specify calibration
interval. This interval (in seconds) is used to periodically
call work that will perform oscillator frequency measurement.
For XTAL32K settle time can be provided in device tree.
After this time (depending on actual oscillator used)
XTAL32K is assumed to be stable and low power clock driven by
XTAL32K is considered OK for precise usage in bluetooth.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
STM32H5 series lacked support for MCO configuration.
Added SOC_SERIES_STM32H5X to approperiate kconfig MCO source
configurations. Added new MCO sources from H5 series and
updated the clock_stm32_ll_h5.c with MCO configuration.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
LL name for PLL1Q is not the same across STM32G0, STM32WL, STM32H5 and
STM32H7 families. This allows to choose the proper definition depending on
the family.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Create clock_stm32_ll_mco.h file to bring stm32_clock_control_mco_init,
mco1_prescaler, mco2_prescaler, MCO1_SOURCE and MCO2_SOURCE definitions
which were previously in clock_stm32_ll_common.{c,h}. This is done so that
stm32_clock_control_mco_init can be called from clock_stm32_ll_h7.c.
Also update Kconfig.stm32 and add new MCO sources to allow H7 support.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Add support of the dedicated STM32F0 14 MHz HSI clock for ADC.
Also remove ADC clock source selection as it is obsolete.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When the image is chain-loaded, clocks may already by initialized.
The driver was lacking support for already configured HSE and
PLL sources. When CONFIG_ASSERT=y get_startup_frequency was
failing since it did not recognize these sources.
It's the same issue that was addressed in #58109 for stm32u5.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add MMIO mapping for Renesas CPG driver in order to avoid
mappings inside mmu_regions.c file. Remove MMU region for
Renesas CPG driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Delete IRQ lock/unlock calls from 'rcar_cpg_mstp_clock_endisable',
because 'rcar_cpg_mstp_clock_endisable' function is always called
under spin lock.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associative tables for core and mod clocks.
Add possibility to enable/disable any of core clocks which presents
in the associative table.
Add handler for setting rate to driver and use generic rcar cpg
function for getting rate.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associated tables of clocks and API for working with these tables,
from this moment the relationship between clocks and their divider are
built. After set rate of some Core clock, driver has to update all
in/out rates of all childrens recursively. During get/set rate calls
if out rate is unknown, we try to get parent in/out rates and its
divider, in case when parent doesn't have valid in/out rates we get
parent of parent and so on until we get parent with a valid in or out
rates.
Add generic Renesas functions for get/set rate of CPG.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Move cpg log module declare to common rcar cpg file. If the module
consists of multiple files, then LOG_MODULE_REGISTER should appear
in exactly one of them. Each other file should use LOG_MODULE_DECLARE
to declare its membership in the module.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
The clock controller is a singleton controller for all the system-level
clocks (XOSC, PLL, CGM, etc) to provide run-time information to the
peripheral device drivers about the module's clocks.
Clock configuration is not yet supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Because they are needed in SoC power.c, clock control init functions
for all other STM32 series has been exported as global.
This commit exports stm32_clock_control_init function as global for
STM32H7 series as well, making custom power management
implementations for STM32H7 series possible.
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
Add fixed-clock clock control driver. This is a first step towards
making fixed-clocks a first-class citizen in the clock control
framework.
Since the change is hidden behind a Kconfig enable this is opt-in
for now.
Signed-off-by: Moritz Fischer <moritzf@google.com>
According to the stm32h5x product specifications, the values of the
voltage ragulator depends on the system clock as follows:
• VOS0 (Vcore = 1.35V) with CPU and peripherals running at up to 250 MHz
• VOS1 (Vcore = 1.2V) with CPU and peripherals running at up to 200 MHz
• VOS2 (Vcore = 1.1V) with CPU and peripherals running at up to 150 MHz
• VOS3 (Vcore = 1.0V) with CPU and peripherals running at up to 100 MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The source clock_control_sam_pmc.c can not build without the
symbol SOC_ATMEL_SAM_MCK_FREQ_HZ which is contained in soc.h
This bug only shows itself if CONFIG_ARM_MPU is not enabled,
which probably includes soc.h through the <zephyr/arch/cpu.h>
which is not desired behavior.
This commit adds the missing header, making the source build
regardless of CONFIG_ARM_MPU.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is not always the same as CPU frequency.
Referring to the `/cpus/cpu@0,clock-frequency` in DTS to determine
the CPU frequency.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
If you compile this code with Clang it will complain about casting a larger
type into a smaller enum.
```C
zephyr/drivers/clock_control/clock_control_nrf.c:120:37:
warning: cast to smaller integer type 'enum clock_control_nrf_type'
from 'clock_control_subsys_t' (aka 'void *') [-Wvoid-pointer-to-enum-cast]
enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
```
Adding `size_t` to the cast removes this issue. Another option could be to
add `-Wno-void-pointer-to-enum-cast` flag to the compile flags.
Signed-off-by: Sigvart Hovland <sigvart.hovland@nordicsemi.no>
It is possible that stm32_clock_control_init function is started
when the image is chain-loaded and hardware clocks are already
initialized to some state (PLL1).
Currently due to an assert in get_startup_frequency function
(which will trigger k_fatal_halt) the boot will stop on the
early stage if CONFIG_ASSERT=y. This is reproducible for example
with standalone MCUboot and TF-M with MCUboot.
Fixed by adding support for HSE and PLL1 clock sources at
get_startup_frequency.
Signed-off-by: Denis Mingulov <denis@mingulov.com>
BDCR and PWR_CR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F0 and F3 series.
Fixes#56449
Fixup for #56505
Signed-off-by: Kay P <kayo@illumium.org>
If clock frequency was already high and a ahb prescaler greater than 1
was used frequency could temporary become higher than allowed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Updated the code to to invoke reset using PCR block
z_mchp_xec_pcr_periph_reset() instead of resetting
using I2C Configuration register
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
New nrfx release brings change of Low frequency sources symbols
in nrf_clock hal to uppercase. This commit aligns all occurrences.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
If the boot loader already switched the system clock to PLL1 we need
to switch back to HSI first and disable PLL1 before we can configure
PLL1. Otherwise the register writes will simply be ignored and we'll
end up with an inconsistent state.
Most of the code has been recycled from `clock_stm32_ll_common.c`.
Signed-off-by: Sascha Silbe <sascha-pgp@se-silbe.de>
Signed-off-by: Sascha Silbe <sascha-pgp@silbe.org>
