IRQ handling functions are now in interrupt controller.
Enable necessary KConfigs to support CLIC properly.
A nice side effect of enabling RISCV_PRIVILIGED is that
`vector.S` is no longer necessary as common code handles
that.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Fixed order of mepc and _mcause in esf for 32bit stacking.
Added missing stack pointer alignement bit support.'
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
RISCV_PRIVILEGED implicitly depends on INCLUDE_RESET_VECTOR.
Remove that dependency by adding support for SoCs that
do not need the `__reset` stub.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
For more effective code execution on STM32 devices is convenient
to enable flash prefetch buffer.
To be enabled by default, possible to disable using kconfig.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Fixes#71511
Follow-up to #70977
Update the approach by moving the `PROVIDE` directive to a separate
linker script added using `zephyr_linker_sources()`. This makes the
change more likely to propagate to existing samples which are using
CONFIG_CUSTOM_LINKER_SCRIPT.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Move the cache size set calls from soc.c do common loader.c
for all related SOCs. Remove unnecessary includes.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The dependencies should be in a 'depends on' clause.
Also, 'depends on PTP_CLOCK' is redundant because this is
within 'if PTP_CLOCK' already.
Additionally, conditionally include the PTP header in the mac driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Variant chip has different USBPD HW PHY, so FW needs
to apply different downstream CONFIG settings based on
the PHY version.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation and
unifies irq locking code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
# Conflicts:
# soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").
This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces a common API for managing nRF53 SoC network CPU
Force-OFF state.
From the application CPU point of view, the network CPU is a shared
resource used by multiple users. The current solution where every user
controls the network core state directly leads to dependencies between
users and does not scale well.
To address this problem there should be a single entity responsible for
controlling the network CPU Force-OFF signal. This commit introduces
such module.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Add code to clock and release reset signal for USBOTG controller on
RW6xx SOC when USB is enabled, and add KConfig selection to indicate to
build system which USB controller this SOC uses.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IPC has inverted the usage of the state lock API.
In this API semantics, the get method disallow the policy of
using the given state, while the put() release this constraint.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Nordic SoCs use this hook to execute `SystemInit` as early as possible
after ARM core reset. Previously, `z_arm_platform_init` was defined as
assembly code, which would simply jump to the other function.
However, this extra code can be avoided by using `SystemInit` directly
in place of the `z_arm_platform_init` symbol (whenever it's undefined).
This is now done with a linker script containing a `PROVIDE` directive.
This saves 4 bytes of ROM (0-16 depending on alignment) and also makes
it possible to override `z_arm_platform_init` out of tree, if needed.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
We need to use correct SOC name when naming the Kconfig.defconfig*
files.
So we need the following changes:
- mimx8mp -> mimx8ml8
- mimx8mm -> imx8mm6
- mimx8mn -> mimx8mn6
- mimx8mq -> mimx8mq6
Then we also need to take care of qualifiers name. Standard notation
uses "_" instead of "."
e.g : Kconfig.defconfig.mimx8mp.a53 -> Kconfig.defconfig.mimx8ml8_a53
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Checking if the device state is locked is not correct, device runtime
put / get is no longer checking for it and the only place that was
locking device's state was the pm action callback and if the idea
was to protect some concurrent call, using it is not enough.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There is no needed to lock/unlock a device state in its pm action
callback. The power management subsystem should take care of
serialize these calls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Prevent the system from entering runtime idle state during IPC
transactions until the HOST acknowledgment is received.
This patch modifies the IPC mechanism to:
- Lock the runtime idle state immediately after sending an IPC message
to the HOST, preventing the system from entering a low-power state.
- Unlock the runtime idle state once the IPC transaction is acknowledged
by the HOST, allowing the system to enter low-power states if
conditions permit.
The changes ensure that the DSP does not enter a power state that could
interrupt the IPC communication process, maintaining the integrity of
the IPC state machine.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to load without 2nd stage
bootloader.
Update common architecture loader to support all build scenarios.
- simple boot: using single binary application without bootloader
- mcuboot: zephyr port of MCUboot
- application: loaded by the MCUboot
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
DMASEC is set to non-secure by default, which prevents CCM from
accessing secure memory. Change DMASEC to secure.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
