The finish interrupt after the previous transaction is completed may
occur in the next transaction. To do hardware reset at this time could
potentially lead to the failure of the transaction.
Therefore, removing the hardware reset upon completing the transaction
helps to avoid a race condition.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Commit a10fee2d5e (drivers: clock_control: ccm_rev2: add support for
reclocking FlexSPI) introduced the ability to set the FlexSPI
clock frequency at runtime on RT11xx series SOCs. However, this
implementation resulted in the clock frequency being rounded up, not
down. This can result in flash clock frequency violations on some
flash parts, causing the system to crash when running in XIP mode.
Fixes#69088
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When exiting PM_STATE_SOFT_OFF, the primary core state is always
used to restore bootctl register and the clock and power gating
settings.
This can lead to problems if non-primary core is powered up and down
many times before primary core 0 is powered down the first time.
The saved state in core_desc[0].bctl will be null, and as a result-
power gating and clock gating is not disabled correctly for
non-primary cores.
Link: https://github.com/thesofproject/sof/issues/8642
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Executing from RAM sections other than rom/code should cause a fault.
This is tested as part of the kernel mem_protect tests.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add initial support for the VPR RISC-V core found in the new nRF54 SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nrf-regtool is a Python utility from Nordic Semiconductor, which is used
for generating binary files with register values for given peripherals.
It sources the descriptions of peripheral registers from CMSIS-SVD files
(typically ones bundled with nRF MDK).
For some peripherals, such as UICR, nrf-regtool supports parsing values
from devicetree as well, based on the bindings already found in Zephyr.
Currently, this tool is not submitted as a script to Zephyr, but it can
be installed from PyPI.
Having nrf-regtool installed is recommended when working with nRF54H20.
Booting the Application or Radiocore CPU requires flashing not only its
firmware, but also its respective UICR instance. On this SoC, the UICR
is used to assign ownership of global hardware resources, including
memory and peripherals, to individual cores. The Zephyr build system can
call nrf-regtool to generate the UICR based on devicetree, to reflect
the boot-time hardware configuration required for a given application.
The generated `uicr.hex` is then merged with `zephyr.hex`, so that they
can be flashed together using west.
The build system integration takes the form of a CMake package, which
includes a version check and reusable components; over time, some of
these components can be reused by sysbuild. This package is located in
the `hal_nordic` module, because it depends on the `SOC_SVD_FILE` CMake
variable, which is defined there as well.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add nrfx and Kconfig related infrastructure plus SoC initialization
code to allow building for nRF54H20 targets (Application and Radio
cores).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to cover missing __ICACHE_PRESENT and __DCACHE_PRESENT symbols that
should be defined in MDK files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Consistently use `zephyr_library*` cmake functions for all nRF Series
and set the Cortex-M linker script in a common place for all of them.
Remove no longer needed include directories.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In nRF54L15 FICR can be accessed also from non-secure code,
so it does not have NRF_FICR_S defined.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
NRF_RTC_TIMER will not be a default timer in the next
version of Nordic timer. It should be soc selection specific.
Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
The RA_PINCFG macro is used to generate a value that can be written
directly to the pin function select register. In addition to the pin
function this value also contains port and pin number information,
located in bit fields that are unused by the register. The bit field
used to store the port information consists of 3-bits. However, a typo in
the mask definition limited the field to two bits meaning only ports 0-3
could be configured. This patch resolves the issue, allowing ports 0-7 to
be configured. If the port is greater than 7 another field (port4) is used
to store an additional bit (allowing an additional 8 ports to be
supported). However, use of this field has not yet been implemented.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
SOCFPGA_SYSMGR_REG_BASE base address now read from Device tree
This commit changes the way the SOCFPGA_SYSMGR_REG_BASE base address is
determined. Previously, the address was hard-coded in the system_manager
source file. This commit changes the code to read the address from the
Device tree. This makes the code more flexible and allows the base
address to be different for different boards.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
In pm_state_set we can't just call k_cpu_idle() because
this will clear out PS.INTLEVEL. Use k_cpu_atomic_idle instead
since Zephyr's expect interruptions to be locked after pm_state_set.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We are arbitrarily setting a value to PS after power gates and
losing valid information like OWB, CALLINC and INTLEVEL.
We need to properly save/restore them to avoid possible wrong behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
ROM configures the ISP boot pins as gpio to determine what boot mode to
be in. But some ROM revisions have a bug where they do not restore the
reset state of these pins before booting application. This can cause
power leakage on these pins and is not an intended configuration from
Zephyr user/board point of view, so restore the reset state as part of
early SOC init (disable the pins). Configuration of pins should be
left up to app/board devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The OpenTitan PLIC has support for up to 255 interrupt vectors, so
set it to that. Previously was set to number of IRQs used.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Only when CONFIG_MP_MAX_NUM_CPUS > 1, then .bss is put in
uncached region. Otherwise, .bss is in cached region.
So the assertion that g_key_read_holder must be in uncached
region must take into account how many CPUs are enabled on
build.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit 3b99fb1b4a ("xtensa: do not imply atomic ops kconfig") removed
ATOMIC_OPERATIONS_ARCH at xtensa arch level. This triggers a bug in
intel_adsp cavs builds with XCC compiler as
CONFIG_ATOMIC_OPERATIONS_BUILTIN is not defined but neither is
CONFIG_ATOMIC_OPERATIONS_ARCH anymore, resulting in failed builds.
Fix the XCC build by defining CONFIG_ATOMIC_OPERATIONS_ARCH at
soc level.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This allows to link code and data blocks, e.g. the vector table, into
tightly coupled memory using `zephyr_linker_sources`.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
With the introduction of the SAI and EDMA drivers, there's
no longer a need to map the MMIOs using the mmu_regions.c
method since this is taken care of by the drivers via
device_map(). As such, remove entries for EDMA and SAI from
mmu_regions.c.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
use CONFIG_SOC_INTEL_ACE15_MTPM instead of CONFIG_ACE_VERSION_1_5.
CONFIG_ACE_VERSION_1_5 leaked from SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add functions to Atmel SAM SoC PMC API. This is an effort to hide
most of the internal registers used in different SAM families.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The clock z_arm_platform_init hangs switching between clocks when using
MCUboot. This fixes the issue using the 8MHz internal clock as gclk_main
source when configuring PLL/DFLL.
Fixes: #67220
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The HAS_SPI_DW Kconfig is rather unncessary. If the synopsys designware
spi is to be included. It should come from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some definitions were only used in soc.c, there's no need to expose them
in a public header like soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
<soc.h> is needed to pull some APIs defined in soc.h.
<fsl_device_registers.h> is needed to access EVENT0/1 addresses.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch enables time stamping controlled by DSP Timers / Time Stamping
logic on ACE1.5 / ACE2.0 platforms.
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
The soc.c interrupt-related definitions are supposed to
provide support for multi-level interrupts. At the moment,
the way the functions work is they only process the LEVEL 1
interrupt from the encoded INTID and treats the provided INTID
as if it were simply a LEVEL 1 interrupt, which is wrong. Another
issue with soc.c is the fact that the definitions from it clash
with the ones provided by the IRQSTEER driver. To fix this, remove
the soc.c file altogether and change the corresponding CMakeLists.txt
to only contain the necessary statements.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
With GCC 12.3 and binutils 2.40, the build fails with:
<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S: Assembler messages:
<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S:51: Error: junk at end of line, first unrecognized character is `n'
<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S:133: Info: macro invoked from here
Because the SOC_ON_EXIT_CPU_IDLE macro puts all the statements on a
single line, there must be a semicolon after .rept
Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Since it takes 400 bytes of code and it is rarely used disable
by default this feature.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If CONFIG_LEGACY_CLIC is disabled, i.e. we adhere to the current CLIC
spec, the mode bits of mtvec have to be 0x3. Everything else is
reserved. Therefore if CONFIG_RISCV_VECTORED_MODE is enabled, the
current implementation is correct. If CONFIG_RISCV_VECTORED_MODE is
disabled, the mode bits have to be set, too.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.
Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.
Note: it is possible to change voltage only for SD/MMC pins on r8a77951
and r8a77961 SoCs.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Setting IT8XXX2_EGPIO_EEPODD bit will disable EGAD pin output driving
to avoid leakage when GPIO E1/E2 on it82002 are set to alternate
function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
When exiting power gated state, call the CPU start function
passed to arch_start_cpu().
Signed-off-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The place where TF-M places its non-secure api header files has changed
Therefore changing it for for all applications that use it.
Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
Clock DMIC0 from the audio PLL when DMIC driver class is enabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Use 'switch' to emphasise that we're handling different values of
'state' in pm_state_set().
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
'ret' in pm_state_set() is always set before it's used, no need to
initialise it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP.
GPIO pinctrl, read/write and interrupt is supported. Runtime mmio
configuration is enabled, so no need for region definition in
mimx9/mmu_region.c
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
pm_device_runtime_get() must be called after pd_intel_adsp_init() is
called for each device, because the latter calls
pm_device_runtime_enable(), which sets the device runtime PM use
count to 0. The current wrong calling order causes a DSP panic
because of an unbalanced pm_device_runtime_put(). Fix this by
delaying pm_device_runtime_get() until the POST_KERNEL initialisation
step.
Fixes commit c3a6274bf5 ("intel_adsp: ace: power: Prevent HST
domain power gating")
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Now that:
1 - LS Clocks sources values are identical accross series
2 - We're able to extract this value from device tree
define STM32_LPTIM_CLOCK choice symbol from device tree
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
For a CLIC the vector table has to be aligned by 512 bytes, if there are
between 65 and 128 interrupts, which is the case for the gd32vf103.
`isr_wrapper` has to be aligned to 64 bytes, s.t. the lower 6 bits of
mtvec are 0.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
For a proper initialisation, the soc-specific `__nuclei_start` has to
be executed before the common `__start`. To ensure that `__nuclei_start`
is linked first, I added the linker section init.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
A lot of the entry.S is again implemented in common/vector.S.
I removed everything redundant and changed the jump to the common
symbol __start at the end.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
.bss and .data are uncached in Zephyr builds for intel_adsp. No need
to try to manipulate cache of objects in those sections.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The MCAUSE register has the "Interrupt" flag defined defined at XLEN-1
position (31 for 32-bit, 63 for 64-bit). This is not an SoC specific
option, and there's no need to expose it publicly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Commit 447a492 switched to `sys_cache*` to enable caches at SoC init. To
preserve the old behavior of enabling caches at init, is missing to
select `CONFIG_CACHE_MANAGEMENT`.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since d992683db5 (soc: arm: replace redundant config option for
caches for nxp_imx), RT1xxx series will not have cache enabled at boot
unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance,
enable CONFIG_CACHE_MANAGEMENT by default.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.
The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the redundant cache config options for kv5x and use
the sys_cache* functions to enable the caches. This will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache* for enabling the caches in nxp_s32. This automatically
considers CONFIG_CACHE_MANAGEMENT and will activate the
cases only if this is active.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This option is no longer needed, all SoCs have been moved out from
soc/riscv/riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganized as follows:
- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)
Also moved out of riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.
[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
fpga-and-soc-design-tools/mi-v
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganize following the hierarchy found in the vendor website [1]:
- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518
Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].
[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
B91_Generic_Starter_Kit_Hardware_Guide/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When Power Management is enabled (CONFIG_PM=y),
the CONFIG_IDLE_STACK_SIZE of 320 is not enough :
Increase its size to 512.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The defconfig.series file for the stm32f4 incorrectly redefines
the PM Kconfig in order to select two dependencies, COUNTER and
COUNTER_RTC_STM32_SUBSECONDS, instead of setting a default for
them if PM is included.
This commit fixes the error described above.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Currently SOF has disabled CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE option and
use pm_suspend_devices() to suspend and resume IPC device during D3
power flow. The pm_suspend_devices() function skips suspending devices
that are busy. In very rare cases, the IPC device is busy during the
power state transition, which results in the device not being restored
during reboot. This happens when FW sends a message to the HOST and
waits for ACK, and the HOST simultaneously sends a SET_DX message to the
DSP. This suspend/resume logic in IPC driver does not work well when the
system enters the D3 state because it is not a suspend state, but rather
a power-off. IPC does not require suspending, only reinitialization when
exiting D3. We cannot avoid this one missing ACK and it cannot block the
DSP from turning off.
When FW receives a SET_DX message it checks whether it can enter the D3
state and then returns an error (via IPC) or calls the pm_state_force
function. Success response is sent directly from power_down assembly and
not via ipc driver. This is because after receiving the response, the
HOST will turn off the DSP.
In order for the transition to D3 to take place, only the primary core
can be active, all pipes must be stopped (and therefore all modules in
FW). The only active thread at this time is the Idle thread. Driver on
the host will not send another ipc because is still waiting for
response. FW can try to send only two notification:
- FW exception: from this place there is no return to continue the power
transition,
- log buffer status: skipped, they remain in the queue without being
sent.
I'm moving pm_device_busy_clear(dev) from IRQ handler to
intel_adsp_ipc_send_message function so the pending ACK does not block
power transition.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
HDA DMA driver uses an excessive value of 128 bytes as required alignment
for DMA buffer size. This may result in the correct buffer size (e.g.
32-byte aligned, which is DT-compliant) being silently truncated before
writing it into DGBS register. This patch changes the requirement to the
value implied by DGBS register format (effectively reduces to 16 bytes).
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
The previous implementation of the sys_arch_reboot function
for the Atmel SAM series was using NVIC_SystemReset.
This caused a reboot time of around 20 seconds on a SAM4SA16CA,
which is now reduced by directly writing to the
reset controller control register (RSTC_CR).
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
QEMU MMU tracing showed that there might be something wrong with
its Xtensa MMU implementation, which result in access violation
when running samples/userspace/hello_world_user.
Here is the MMU trace from QEMU from failed runs:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00103050, ret = 26
The place where it fails is during reading from 0x109014.
From the trace above, the auto-refill maps 0x109000 correctly
with ring 0 and RW access with WB cache (which should be correct
the first time under kernel mode). The page 0x109000 is the libc
partition which needs to be accessible from user thread.
However, when accessing that page, the returned physical address
became 0x103050 (and resulting in load/store access violation).
We always identity map memory pages so it should never return
a different physical address.
After forcing TLB invalidation during page table swaps, the MMU
trace is:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
get_pte: autorefill(00109028): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109028): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
get_pte: autorefill(00109014): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109014): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00109014, ret = 0
xtensa_cpu_tlb_fill(00109020, 0, 0) -> 00109020, ret = 0
Here, when the same page is accessed, it got the correct PTE
entry, which is ring 2 with RW access mode (but no cache).
Actually accessing the variable via virtual address returns
the correct physical address: 0x109014.
So workaround that by forcing TLB invalidation during page swap.
Fixes#66029
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need for this config here and it is messing
with total sys heap calculation.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Supporting Stop1 mode while BLE RF is enabled requires some specific
adaptation and usage of STM32WBA Cube BLE controller scm API.
scm (Secure clock manager) is in charge of switching clock depending
on RF status and should be informed of PM stop modes scheduling.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32WBA controller uses a PKA driver to perform cyphering operations
on keys. Since PKA hardware block requires RNG clock to be enabled, a
synchronization with zephyr RNG driver is needed.
Use RNG enable status to check if RNG could be switched off or needs to
be switched on.
Similarly in entropy driver, don't cut RNG clock if PKA is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The DC233C core has support for both i-cache and d-cache.
So mark it as such so we can test caching of Xtensa in QEMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Definition of ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT,
which is used in the intel_adsp_force_dmi_l0_state function,
is missing.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
Currently on zephyr, RAIL library is used only by Bluetooth applications,
with this update, it will be able to be used for sample applications
for custom radio phys.
All files were copied from Silicon Labs GSDK v4.2.4.
Signed-off-by: Zoltan Havas <zoltan.havas@silabs.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Separating two new functions force and allow l1
to have the current state with separated functions
in the ipc file so that SOF can call these
functions via IPC DMI_FORCE_L1_EXIT. Change related
to the addition of a new parameter to force
DMI L1 exit on IPC request.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This follows the idea to remove any z_ prefix. Since MMU has
a large number of these, separate out these changes into one
commit to ease review effort.
Since these are no longer have z_, these need proper doxygen
doc. So add them too.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Use the already available in the tree mechanism of adding assembly
instructions right after WFI/WFE to implement the workaround for
nRF5340 anomaly 168 (replace the 4 NOP solution used on the network
core as it turned out to be insufficient) and provide two related
Kconfig options so that users are able to adjust the workaround to
their actual needs (disable it entirely or use it in the extended
version).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Enable the TF-M NS storage partition for nordic boards.
This partition is otherwise not used, and configured as secure.
Fixes: #59376
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
