Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Add a VEVIF node to be used for communicating with SysCtrl (cpusys).
This is the only part of the SysCtrl VPR exposed to local domains.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
If I2C3 switches from GPH1/GPH2 to GPB2/GPB5, extend setting
is required.
Test: Accessing I2C is normal if I2C2, I2C3, I2C5 are switched.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add definition of the nRF54H20 SoC with its Application, Radio,
and Peripheral Processor (PPR) cores and an initial set of
peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
These list of files add basic support for StarFive
JH7110 SOC Device Tree includes for VisionFive2
board.
Signed-off-by: Pratik Farkase <pratik.farkase@wsisweden.com>
Add a new nodes for PPR's VEVIF. In app cores, VEVIF registers are part
of the VPR peripheral, so it is exposed as a child node (since it
requires its own properties, eg #mbox-cells). In VPR, it's a CPU child
since it's not a memory-mapped peripheral, but used with CSRs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.
As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct
asserts when a pin is provided. Note that default is 32, correct for eg
FE310.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.
Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Microchip's PolarFire SoC has a total of 9 contexts associated with the
Platform Interrupt controller (PLIC). the E51 core has a single context
(M Mode), and the application processor U54 cores have two each (M mode
and S mode, respectively)
While we are at it, there are a total of 186 interrupts, not 187.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Microchip's PolarFire SoC (device family name: MPFS) is not specific to
the Icicle Kit. Rename the devicetree sources to be more generic and to
align with Linux and allow for other development boards to adopt.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
When the alternate setting is configured as func3, in addition to
the setting of func3-gcr, some pins require external setting.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
