DW watchdog driver is not used on ACE,
Intel ADSP watchdog driver will be used in DTS when ready to use
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding for nxp,mrt and nxp,mrt-channel. MRT is
NXP multirate timer, a simple timer with multiple
independent channels.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit introduces all changes necessary for utilizing
the serial interface on i.MX8QM/QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since the LPUART peripheral DTS binding requires the
"interrupts" property be specified even if it's not going
to be used for now we need to add a dummy interrupt controller
node to make that possible. Logically speaking, this dummy
interrupt controller should be used by peripherals which
can assert interrupts directly routed to the DSP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Generic GPIO enabled analog switch to isolate devices from an I2C bus
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Replace spsc_pbuf with pbuf implementation dedicated to
be used by IcMsg based backends.
The pbuf is written on top of simple read/write semantics
with minimal footprint and code complexity
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
The `int1-gpios` property is common for both spi and i2c
implementations of adxl372. Therefore move it to
`adi,adxl372-common.yaml`
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Add basic support for ams TSL2561 light sensor. Triggers, attributes
and manual integration time are currently not supported.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
This device lost the reg property since 88c9d1fbaf, causing the
nucleo_l011k4 board to not build anymore. Add it back, 512 bytes should
be the right number for this chip.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Both the BQ27421 and BQ27427 have a few preset Chemistry profiles.
For the BQ27421 there exists three variants of the IC, and for the BQ27427,
it can be configured. The chemistry profile among other things includes the
taper voltage, which is used to detect charge termination.
This adds an optional `chemistry-id` config option to the driver. On the
BQ27421, it will confirm that the correct variant of the IC is mounted,
and on the BQ27427, it will configure it with the correct value.
Side note: The reference manual for the BQ27427
(https://www.ti.com/lit/ug/sluucd5/sluucd5.pdf) currently contains some
errors and inconsistencies regarding these registers. The table on page 7
appears to be correct.
Signed-off-by: Tobias Pisani <topisani@hamsterpoison.com>
Added initial version of Infineon AIROC WIFI driver
Added initial version of binding file for Infineon AIROC WIFI
driver
Rename CONFIG_ABSTRACTION_RTOS_COMPONENT_ZEPHYR to
CONFIG_USE_INFINEON_ABSTRACTION_RTOS
Exclude cy8cproto_062_4343w platform from
drivers.modem.esp_at.build test
Change revision hal_infineon to
69c883d3bd9fac8a18dd8384624b8c472a68d06f
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix the following compilation warning:
```
Warning (unit_address_format): /memory@0xb0000000: \
unit name should not have leading "0x"
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
The variants of this family have different sizes of eeprom. This moves
eeprom definition from common family definition to device specific.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Add in DT the possibility to configure both INT1 and INT2
pin. The driver will then assign one of the two (either 1
or 2, according to what value drdy_pin is set) to a gpio
for receiving drdy interrupts.
The other pin may be used in the future to receive event
interrupts.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The HCI receive path has a delay between reading the header and payload
from the controller to give the controller time to setup the SPI
peripheral for the next transaction. Add the same delay on the transmit
path for the same reasons.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Real UARTs usually write 1 to a few bytes at a time through a
latch buffer. Add latch buffer property to binding for
uart_emul and limit fifo_read and fifo_fill to not exceed the
latch buffer.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Maxim MAX20335 is a PMIC with Ultra-Low IQ Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
