This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Add device driver for TI TMP114 I2C temperature sensor.
The driver only support basic functionality, i.e. fetch temperature
using default values.
Datasheet:
https://www.ti.com/lit/ds/symlink/tmp114.pdf
Signed-off-by: Fredrik Gihl <fgihl@hotmail.com>
For historical reasons, inversion mode is enabled by default in the
current implementation. This commit introduces an `inversion-off`
boolean DTS property, allowing it to be disabled if necessary.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Adds support for the PGOOD pin. This pin is asserted by the
regulator when converter startup has completed and the output
is stable. If the PGOOD pin is not used, the PGOOD state is
check via the PGOOD_PIN_STS bit.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Deprecate the use of location_* properties in the i2c_gecko driver
and migrate to the pinctrl api for enhanced maintainability and
compliance with current standards.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Enable serial communication through UART port between HDMI ports.
Signed-off-by: Myeonghyeon Park <myeonghyeon@tsnlab.com>
Signed-off-by: Junho Lee <junho@tsnlab.com>
This property will allow PWM driver allocate data buffer
in appropriate memory region.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Squash the two copies of this file found in `dts/arm` and `dts/arm64`.
Their contents were identical up to devicetree property ordering.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This file was moved to the `dts/arm64` directory 3 years ago:
3539c2fbb3
However, the original file in `dts/arm` was left by mistake. Since then,
it's been unused and seldom updated, but it hasn't diverged much.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Driver already handles the case when 'reset-gpios' is not provided, so
remove 'required: true' from bindings to allow boards / shields definition
without reset signal being connected to any Zephyr controlled GPIO.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the management
of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This file is basically a copy of the AM62x M4 dtsi but an
additional mcu_uart1 interface.
The internal clock frequency feeded into the UART IP is
96 MHz instead of 48 MHz, which is different to the AM62x.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
We define two frequencies in the am62x_m4.dtsi file.
Use DT_FREQ_M for both frequency to make them more
human-readable and easier to understand.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The commit restricts erase-value to either 0xff or 0x00.
On program-erase type devices writes can only change from
erase value of bit to opposite, ease usually consists of two
operations which is programming the opposite value to every bit
of erase range and then turning back all bits to the "erase-value";
above makes it impossible to have erase value of device to be other
than 0xff or 0x00.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
add gpio_intel driver with acpi based resource enumeration support.
Also updated test cases overlay with new dts entires.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
