Mark counter as supported for nRF54L15 to allow running
counter_basic_api by twister.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
This commit enables the IRQSTEER interrupt controller
on NXP's XTENSA-based i.MX8QM and i.MX8QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Adds i2c3 on the dts of nucleo_f401re.
Adds necessary overlay and nucleo_f401re in i2c_target_api test case
to enable the board.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
cpuapp/cpurad can be debugged using the J-Link runner.
Note:
This feature is still experimental and has known issues. For example,
setting a breakpoint to main requires to patch init.c with a loop
polling a variable so that we stop there until unset from GDB.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add Open Alliance spi protocol support.
Open Alliance is a chunk-based SPI protocol, based on sending
over SPI an ethernet frame divided in smaller chunks, using a
specific 32-bit header for each chunk transferred. All chunks
can be sent or received by a single dma transfer.
Default mode is set to Open Alliance SPI without protection,
since the adin2111 dev. board comes shipped this way.
Tested:
- Open Alliance SPI, no protection (default board shipped)
- Open Alliance SPI, protection
- Generic SPI, no crc
- Generic SPI, with crc8
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Nordic Semiconductor no longer offers support for this board, so warn
users to avoid it for new prototypes.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
In order to avoid defining almost the same overlays for different
sample codes and/or applications a common overlay file per
display interface is defined under the boards dts folder.
In doing so, an application/sample code will only have to
define another overlay explicitly under application's board
folder if more blocks are to be enabled. In either case, users
should explicitly invoke the requested overfiles at 'west build'
invokation by using the DTC_OVERLAY_FILE system variable.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add build_only for the st,stm32-ethernet driver to the build_all
ethernet tests and add an entry for ethernet support to make sure
ethernet driver is built.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Enabled the PIT and Multi channel support
for some of the rtXXXX devices.
- rt1010
- rt1060
- rt1160
- rt1170
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add `pico_serial` which is alias of `uart0` as a definition
related to pico_header.
The uart0(GP0 and GP1) is shown as default serial port
in pinout diaglam.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
For sharing pin definition property with `worldsemi,ws2812-gpio`,
rename `output-pin` to `gpios`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit fixes#67277 and hence adds possibility
to properly utilize grove extension port.
5V_BUS can be enabled via regulator bus_5v. By default this
regulator is disabled.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml
has needless `_` in filename.
Renamed it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Update board's DTS configurations to support the Renesas MIPI DBI
host controller.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Re-assign peripherals' default pins functionality to avoid
conflicts with LCD controller's pins usage. The PRO DevKit
exhibits a display socket which is routed to dedicated pins.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This adds the minimal get_time/set_time support for the rp2040 and
enables support by default on the Pico boards. This doesn't support
configuring the clock source or alarm interrupts yet.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
pty is not available on Windows hosts. Running a sample in Qemu
on Windows shows an error. Fix it by enabling pty on Unix hosts only.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add `zephyr,ipc-icmsg*` nodes, with mboxes specified in a common file.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Partetas <gerard@teslabs.com>
Add IPC shared memory regions in the global RAM, as well as an enlarged
SRAM region for Application core.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Set status = "okay" for temp device tree node to allow use
of nRF 802.15.4 Radio Driver on the nrf54l15pdk_nrf54l15_cpuapp board.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Set status = "okay" for ieee802154 device tree node to allow use
of ieee802154 on the nrf54l15pdk_nrf54l15_cpuapp board.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
fix QSPI NOR flash is25wp064a input page programming to 32h
as 38h isn't functional. Also adjust the frequency to max
possible value from nRF52 as 32MHz as the flash supports upto
133MHz.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add CMake code that fixes west attach on nrf54l15pdk_nrf54l15.
I don't know why this fixes west attach as this is cargo cult code.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Generate `boards/deprecated.cmake` entries to map all legacy boards to
their HWMv2 incarnations.
Single-SoC, single-CPU boards, whose names haven't changed, don't need
to be listed here. In those cases, `BOARD=<name>` counts as a shortened
form of `BOARD=<name>/<soc>`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Emulate SERIAL_SUPPORT_INTERRUPT for UART_NATIVE_TTY, using a thread that
polls the tty and invokes the callback.
This allows interrupt-driven subsystems such as modbus to use a native tty,
which is useful for testing purposes.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
The amount of RAM owned by PPR core is quite limited, making it
difficult to fit many samples. Instead, use execution in place and
increase its code partition from 28K to 64K (as now it doesn't have to
match RAM size).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This is a setting that depends on the board or application, so it should
not be part of SoC definition files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since bd9836be8c
the native logger is enabled always (even if a UART is present)
as it was though more conveniant for users.
But the documentation was not updated to reflect this.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The UP Squared board comes with different CPUs where Atom ones
run at 1.6GHz while the Pentium and Celeron ones run at 1.1GHz.
Since the APIC TSC Deadline timer driver is tied to the CPU
speed, and we were using 1.6GHz as the hardware clock speed,
real world time would not be correct for Pentium and Celeron
based boards (i.e. 1 second sleep requested in application does
not translate to 1 second in real world). Change it to use HPET
timer instead as HPET has the same clock rate for all board
variants. Applications requiring more precise clock rate can
override this in their configuration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Support of stm32h5 targets with pyocd is required to allow debugging.
Provide runner configuration and update board documentation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Commit 940c66f82e added a bunch of
ACPI PNP ID to x86 boards but skipped those for ACRN. And commit
34a2fbfba1 changed the behavior of
PCIe controller to looking for PNP ID, it results in compilation
error due to build asserts. So add the PCIe controller node to
the ACRN base DTS file.
Fixes#68956
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nRF54* SoCs are in a very early stage of production and the software
supporting them is to be considered experimental. Document this
accordingly in the respective boards.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
If slots partitions are defined, related chosen should be configured.
Fixes build issue in samples/subsys/usb/dfu
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Prevent overrunning the irq vector table.
This is not happening today in tree, but coverity thinks it
may. Checking for it to prevent it is not a bad idea
anyhow, so let's do it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
i2c pads were incorrectly configured and failed to work when testing
against an external fram part. Correct the i2c pinctrl settings for
arduino i2c to match other boards in the mimxrt lineup.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The yaml uses `arch: riscv` while other boards specify either
`arch: riscv32` or `riscv64`.
Unify this by changing the value to `riscv32`.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Previously the boot_write_img_confirmed() function used the MCUboot
public API function boot_set_confirmed(), but this function is hardcoded
to set the confirmed flag of slot 0. This works for MCUboot swap modes
but not for Direct XIP, where applications can execute out of secondary
slots.
This commit changes boot_write_img_confirmed() to instead use
boot_set_next() which sets the confirmed flag for a given flash area
and works with Direct XIP.
DT_CHOSEN(zephyr_code_partition) is used to get the current partition.
The zephyr,code-partition chosen node must be defined.
This commit also adds the zephyr,code-partition chosen node to the
native_sim devicetree to allow the tests under tests/subsys/dfu to
build for this target.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
The DRAM range 0xc0000000~0xcfffffff is reserved for the Ethos-U NPU,
so change the RAM base to 0xd0000000.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
remove legacy modem properties and add modem node
compatible to modem subsystem, rak5010_nrf52840
has two variant, one with BG95-M3 and other is
BG96 modem, both are pin to pin compatible.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Define the reg and size property for the stm32 disco kits
which have an octospi instance
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
Also remove the <size> property for the stm362h750 disco kit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add a board that allows to build for the nRF54H20 PPR RISC-V core.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add targets that allows building for the Application and Radio cores
in the nRF54H20 SoC on the nRF54H20 PDK board.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The mailbox peripheral is actively accessed by stm32_hsem functions,
so mark the device as enabled in DTS.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Define the reg and size property for the stm32 boards with qspi inside
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Define the reg and size property for the stm32u585 and stm32l562
disco kit.
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
The stm32l562 reads the sfdp table from the flash itself.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
The DMA is already enabled for this board, but updating the board doc
page to make that clear, and enabling the DMA loop_transfer test.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add support for ADI EVAL-ADIN2111EBZ.
Tested samples:
* hello_world
* blinky
* dhcpv4_client
Co-developed-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Add support for ADI EVAL-ADIN1110EBZ.
Tested samples:
* hello_world
* blinky
* dhcpv4_client
* adt7420
Tested proper SPI detection of the ADIN1110 chip.
Co-developed-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Microchip's PolarFire SoC interface with on-board spi
nor flash via system controller. This on-board spi nor flash can be
used to store FPGA design bitstream's.
Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
qemu_x86_tiny@768 has coverage enabled by default. Because of
this, it requires more stack space for running tests.
The increases needed are verified via twister.
Fixes#68272
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
We need to enable this configuration for all R-Car ARM64 boards.
First and foremost, we definitely should run Zephyr on the boards
in the NS-EL1 state. The EL3 is used for TF-A, EL2 is used for
U-Boot, and Xen in the case when we run Zephyr as Dom-0. The S-EL1
is used for OP-Tee, and S-EL0 is used for OP-Tee apps.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
On the Polarfire SOC Icicle Kit the SPI pins are routed to MikroBus.
Enable SPI by default.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
the device tree offers a default config (qdec0) for 1x qdec at TC0,
however does not offer a default config for qdec1 - qdec3.
this will be added with this commit. Fixes#65610
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
The purpose of this separation is to avoid conflict initializing
gpio-keys because button 0 and joystick up have a shared interrupt
source. Joystick is now configured using polling mode option.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
This allows to run tests & examples on the physical board with:
```
west twister -p mps2_an521 --device-testing --device-serial /dev/ttyUSB0
```
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Create a folder for RZ Renesas range device tree to follow how it's
done for other renesas ranges.
It will also help to better delimit areas to maintain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
- Remove hadcoded cc2538-bsl.py path
- Use cc1352-flasher program instead
- Add docs about how to install the program
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
This commits makes it possible to use the onboard bluetooth
module (STM32WB5MMG) with existing zephyr bluetooth samples.
Note that there was no hardware flow control wiring
available on the board, which is why it has been disabled
in the both main board and BLE module Device Tree. As the
board doesn't support HW flow control, users must set
CONFIG_BT_HCI_ACL_FLOW_CONTROL=n in project files.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
This patch introduces the Bluetooth Low Energy (BLE) feature to the board.
The board utilizes the STM32WB5MMG as the BLE module. However, As there
was no BLE controller available for this module. Therefore, a board
support package has been added to enable the STM32WB5MMG module to act as
a BLE controller. This is achieved by running Zephyr's hci_uart example on
the STM32WB5MMG module which enables communication with the main
microcontroller over the H:4 HCI transport protocol. So, users must first
build the BLE controller for the BLE module and upload it via on board
ST-Link,then they can uses Zephyr Bluetooth demos on the development board
Note that there was no hardware flow control wiring available on the
board, which is why it has been disabled in the both main board and BLE
module Device Tree.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
OpenOCD can now be used to flash and debug nucleo_wba52cg.
However it required use of STMicroelectronics OpenOCD fork.
Add instructions on how to use it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This reverts commit 6a3612666e
"boards: mps2_an385: Exclude platform from networking tests"
This would have found the issue described in #67762 where a
network test was failing because of wrong section placement.
All the simulated environments (qemu_x86 and native_sim) used
in network testing missed this problem, but could have easily
found if network tests would have been run in mps2_an385.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Instead of relaying on those macros having been defined
somewhere else let's define them for this library.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This constant is supposed to be defined as a long instead of an int,
presumably to support systems where int isn't large enough.
Signed-off-by: Keith Packard <keithp@keithp.com>
Define the pinctrl-based pin controller instance
for the Mercury XU board and remove the old implementation
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
Setting an extremely low value by default on two boards doesn't seem
like the right thing to do. The defaults were added with the v1 logging
subsystem in https://github.com/zephyrproject-rtos/zephyr/pull/8023.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Provide three basic examples to test the x-nucleo-iks4a1 shield:
- Test shield in standard mode
Acquire sensor data from shield with all MEMS sensors connected
to micro-controller
- Test shield in HUB1 mode
Acquire sensor data from shield with lis2mdl and lps22df
connected to LSM6DSV16X sensor hub
- Test shield in HUB2 mode
Acquire sensor data from shield with lis2mdl and lps22df
connected to LSm6DSO16IS sensor hub
Signed-off-by: Armando Visconti <armando.visconti@st.com>
x-nucleo-iks4a1 shield is an arduino compatible companion board
which can be used on top of Nucleo standard boards for industrial
applications. Following MEMS sensor are currently supported:
- LSM6DSO16IS: MEMS 3D accelerometer + 3D gyroscope
- LSM6DSV16X: MEMS 3D accelerometer + 3D gyroscope
- LIS2MDL: MEMS 3D magnetometer
- LPS22DF: Low-power and high-precision MEMS pressure sensor
(https://www.st.com/resource/en/data_brief/x-nucleo-iks4a1.pdf)
The board exports three overlays:
1. x_nucleo_iks4a1.overlay (standard mode)
All MEMS sensors are connected to micro-controller.
2. x_nucleo_iks4a1_shub1.overlay (HUB1 mode)
LSM6DSV16X IMU sensor act as a sensor_hub with LIS2MDL and
LPS22DF connected to it.
3. x_nucleo_iks4a1_shub2.overlay (HUB2 mode)
LSM6DSO16IS IMU sensor act as a sensor_hub with LIS2MDL and
LPS22DF connected to it.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The nucleo_g0b1re board is based on stm32g0 that supports 2 can
controllers. This commit adds support for the second can controller.
Add also can label in yml board file.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This patch add the basic board support for the
STM32WB5MM-DK Discovery Kit. At the moment only
debug UART Debug is ported. Other peripherals will be added
in the following patches.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
In order to build a BLE application nucleo_wba55cg fecthing controller
blobs is required. Document the command.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Let's not treat this driver differently for simulation
than for real HW.
There is a few cases which are not yet working,
but the driver is disabled by default for all platforms.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CONFIG_RISCV_SOC_INTERRUPT_INIT=y and CONFIG_RISCV_HAS_PLIC=y are both
defaulted to y by the board SoC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Decrease total RAM usage when Wi-Fi is enabled, specially after
`config HEAP_MEM_POOL_ADD_SIZE_BOARD` was added. This allows application
to handle additional HEAP as required.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
According to the documentation and pinctrl file, sercom0 tx should
be available on PA10C/SERCOM_PAD[2]. However, and somewhat confusingly,
txpo 2 meant SERCOM_PAD[0] with RTS/CTS flow control.
Changing this to txpo 1 uses SERCOM_PAD[2], which allows sercom0
to work as documented.
Signed-off-by: Tom Rothamel <tom@rothamel.us>
Changes:
* Fixed typo in the PWM channel number (32 -> 3)
* Added a prescaler to make the board compatible
with the blinky_pwm sample
Output of the sample before the fix:
PWM-based blinky
Calibrating for channel 32...
[00:00:00.010,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.016,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.022,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.028,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.034,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.040,000] <err> pwm_stm32: Invalid channel (32)
Error: PWM device does not support a period at least 31250000
After the fix:
PWM-based blinky
Calibrating for channel 3...
Done calibrating; maximum/minimum periods 1000000000/7812500 nsec
Presence of PWM signal after the fix
has been confirmed using a logic analyzer.
Signed-off-by: Maksim Salau <maksim.salau@gmail.com>
Prevent overrunning the irq vector table.
This is not happening today in tree, but coverity thinks it
may. Checking for it to prevent it is not a bad idea
anyhow, so let's do it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Prevent overrunning the irq vector table.
This is not happening today in tree, but coverity thinks it
does. Checking for it to prevent it is not a bad idea
anyhow, so let's do it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a new way of passing extra command line arguments
to native simulator based boards using kconfig.
If this new kconfig option is set, its content will be treated
as extra command line arguments/options which will
be parsed before the other command line options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Switch the default MCUBoot FW Update mode from Swap & Scratch
to more preferable Swap & Move for the rest of NXP MCUs.
Other NXP MCU platforms have been already switched.
Delete the scratch partition. Save RAM & ROM.
Slot 0 has one additional sector, for use with
the swap move algorithm.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Update generation comment for NXP board pin control files, to point
users to the current pin control scripting files in NXP's HAL. Note that
these files have not been regenerated- the script name simply has
changed, so update these references to avoid confusion.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
New UART shim must be adapted to work in the simulated environment.
Use legacy version until it is fixed.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Using the recently added WS2812 PIO driver, this enables the LED on the
QT PY to work with the built in RGB LED examples.
Signed-off-by: Ian Wakely <raveious.irw@gmail.com>
qemu_x86_64 has default of 2 CPUs but the device tree only
has 1. For correctness, add another CPU node to the tree.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Update source lib and include path for TF-M interface files.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
The place where TF-M places its non-secure api header files has changed
Therefore changing it for for all applications that use it.
Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
Enable L/R channel pair for DMIC0 on the RT595 EVK. The RT595 EVK has a
pair of MEMS microphones wired to PDM channel 0 and 1, so these channels
are configured with appropriate gain and filter settings for the MEMS
microphones.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This update stm32h747i_disco board display config to use ltdc frame
buffer config feature.
For lvgl, by default ltdc frame buffer number set to 0.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Add flash partitions required to use the board with MCUboot.
Also fix the chosen zephyr,code-partition devicetree node and point it
to slot0_partition.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add flash partitions required to use the board with MCUboot.
Also fix the chosen zephyr,code-partition devicetree node and point it
to slot0_partition.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add the possibility to flash stm32h747i_disco board using west
STM32CubeProgrammer runner, for both cores.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Tested with zephyr example project "samples/basic/blinky" and "samples/
basic/button". These examples can run out-of-the-box. No modification
needed.
for "samples/basic/blinky", the red LED inside RGB LED on board will
blink every 2 seconds.
for "samples/basic/button", the red LED inside RGB LED on board will
turn on once BTN1 on board is pressed down. An log will be present in
uart console as well.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Add a tag to filter slow bsim tests in CI
(or tests which do not provide much extra coverage and
are not worth running all the time in CI)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Speed up the interrupt handler when the MCU is woken
due to a phony interrupt (while busy waiting).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Speed up the interrupt handler when the MCU is woken
due to a phony interrupt (while busy waiting).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CONFIG_STM32_LPTIM_CLOCK_LSE definition is now defined directly from
device tree, remove from boards definition.
Solving systematic warning about CONFIG_STM32_LPTIM_CLOCK_LSE being
selected with unsatisfied dependencies.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Change bin name to esp32_appcpu_firmware instead of
esp32_net_firmware to keep naming coherence.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add support for M5Stack AtomS3 Lite development board.
The AtomS3 Lite is a smaller version of the AtomS3 that
features only a StatusLED and no LCD display.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Adds the device trees, Kconfig, and documentation files.
The following features have been confirmed working on hardware:
* LED
* Button
* UART
Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
Power profiles enable the app to dynamically switch modes and support
DVFS. These profiles leverage the PCA9420 PMIC to change the VDDCORE
voltage, and optimize power consumption. Two runtime profiles are
provided for the application:
* main_clk sourced from FRO192M, VDDCORE at 0.9 V
* main_clk sourced from FRO96M, VDDCORE at 0.8 V
Both profiles use the FRO, and the FRO is retrimmed with the target
frequency when switching profiles.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use a board with a mikroBUS as example in the shield documentation and
update the example application since the board_shell sample was removed in
commit 7c85f4b2f5.
Fixes: #67134
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Include zephyr/dt-bindings/adc/adc.h in the shield DTS overlays to simplify
using this shield in application overlays.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Due to board name change (JUNO -> SBC-3.5-PX30), it is necessary to
update board names, links and references in files and documentation.
Signed-off-by: Ettore Chimenti <ek5.chimenti@gmail.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The mailbox peripheral is actively accesses by stm32_hsem functions,
so it should be marked as enabled in DTS.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
I2S is unused on the dragonclow board. Increase the R division factor
(used for I2S), to reduce the clock frequency, which saves some power.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Update dts files to use ST vendor specific HCI SPI Bluetooth driver.
Remove unnecessary GPIO bias for output pins.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Some GD32 board pictures exceed the maximum allowed limit (100K), so
reduce them.
Automated using `cwebp path/to/board.jpg -o path/to/board.webp`
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adafruit KB2040 has one NeoPixel(WS2812) LED that
attaches to GPIO17 pin.
Add configuration for it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This adds a hint that for stm32h747i_disco just some display shields are
supported.
Signed-off-by: Maximilian Huber <gh@maxhbr.de>
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Reduce a bit the amount of boilerplate by placing common
Kconfig selections in common options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Provide a good enough UART configuration, but do not
select it as backend by default, let apps do that.
The UART and its driver are very heavy compared to
other backends it may replace, so let's avoid
enabling it by default.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Even if the UART is enabled, let's not use it by default,
in this platform, as this UART is not meant for user
interaction, but to connect other devices
(for ex. BT controller).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Now the HW models include the UART(E) models.
So let's allow selecting it, but let's
not default to it, or enable it by default,
as it is only in very rare cases uses will want it,
and some may already be using the native ptty
instead.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
For simulation, we cannot get the UART regiter address
for the pinctrl config structure from DT, as that
cannot match the one allocated at build time.
So let's override it at runtime with the correct address
which is stored in the UART config structure.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Include zephyr/dt-bindings/adc/adc.h and zephyr/dt-bindings/gpio/gpio.h in
the shield DTS overlays to simplify using this shield in application
overlays.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use the common io-channel-cells name "input" instead of "positive" and
"negative" to make this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a small paragraph about the input SDL touch driver,
clarifying the evdev driver is not the only input one.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a small paragraph about the EEPROM simulator,
and improve slightly the flash simulator section
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This is in preparation for xmc4xxx mdio/ethernet patch set. In the
ethernet drivers, the DMA memory (including descriptor and buffers)
must live in dsram1 or dsram2.
Currently, in xmc47_relax_kit the RAM is the psram1 region meaning
that DMA transfers will not work. Switch to using dsram regions instead.
Also, merge dsram1 and dsram2 into a single region since they are
contiguous.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Reorganized as follows:
- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)
Also moved out of riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.
[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
fpga-and-soc-design-tools/mi-v
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganize following the hierarchy found in the vendor website [1]:
- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518
Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].
[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
B91_Generic_Starter_Kit_Hardware_Guide/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Changes to this file were missed out from the original
PR #65564 that added Renode support for this board, add them
here so that it gets ran in CI.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Enable FlexCAN peripheral driver for ucans32k1sic board. The GPIO-based
CAN transceiver driver is used to control the on-board CAN transceivers.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The board uses pinctrl API. This commit updates pin USART pin definition
to be compliant with new API.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
The board uses pinctrl API. This commit updates pin USART pin definition
to be compliant with new API.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This board is similar to 'lora_e5_dev_board', but with smaller form-factor,
which makes it better suited as low volume prototype device.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The RISCV32 Virtual board is a virtual platform made with
Renode as an alternative to QEMU. Contrary to QEMU, the
peripherals of this platform can be easily configured by
editing the `riscv32_virtual.repl` script and the devicetree
files accordingly, this allows certain hardware configurations
that only exist in proprietary boards/SoCs to be tested in
upstream CI.
Added another entry for this board to the excluded platform in
`kernel.timer.timer` test.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The PAN1783A-PA evaluation board is a development tool for the
nRF5340 from Nordic Semiconductor and the third evaluation
board variant for the PAN1783 Module. The power amplifier (PA)
version includes FEM support.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The esp32c3 systimer has been fixed in PR #53453, but stamp_c3 was
not included, so we will update it to catch up with this fix
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add the possibility to flash nucleo-l4r5zi board using west
STM32CubeProgrammer runner.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Corrects the size of the external octoFlash connected to the
mcu of the stm32h573i disco kit from STMicroelectonics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
After adding new GPIOTE instances, there is a need
to enable the instance for individual boards.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Change the GPIOTE driver to HAL to prevent instantiation
issues with a multi-instance GPIOTE driver.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
- board.cmake is augmented for LinkServer (now the default runner
for this board)
- the board's doc file is updated as well
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
- board.cmake is augmented for LinkServer (now the default runner
for this board)
- the board's doc file is updated as well
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
this corresponds to soc/arm/nxp_lpc/lpc55xxx/soc.c:129. also, 16MHz is
used on the lpc55s69-evk.
Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
This commit sets linkserver as the runner, if none was set in the
board's board.cmake file. This change will enable NXP to make linkserver
the default runner for the NXP boards.
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
enable CONFIG_USB_DC_HAS_HS_SUPPORT when we use only OTG_HS
and not OTG_FS.
in that case TEST_BULK_EP_MPS (Endpoint max packet size)
equal 512 and not 64
it is the case for nucleo_h723zg and for nucleo_h7a3zi_q
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Enable FlexTimer (FTM) as a PWM controller for this board. Use the RGB
LED controlled by FTM0 as PWM-LEDs for the samples and tests.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set CONFIG_MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY=y
for lpcxpresso55sxx boards.
Synchronize with their default MCUBoot configuration.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Removes deprecated boards that were added in/before September
2021, which would be prior to the release of Zephyr 2.7.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
When transforming SDL2_LIBRARIES and SDL2_INCLUDE_DIRS into compile
options, each member needs to be preceeded by -l or -I. Use the cmake
list(TRANFORM) operation to prepend the flag to each list element instead
of just prepending the flag to the entire list.
Signed-off-by: Keith Packard <keithp@keithp.com>
Update documentation to include Raptor Lake P and update link to
the correct online datasheet.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Rename old rpl_crb to rpl_s_crb, which is needed for adding other
Raptor Lake boards. Main changes should be in the board device tree
configuration raptor_lake_p vs raptor_lake_s.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The W5500_EVB_PICO is an evaluation board for the Wiznet W5500
ethernet mac/phy based on the Raspberry Pi Pico.
Signed-off-by: Ian Wakely <raveious.irw@gmail.com>
Only reset cause is supported as there is no common unique id
present on those chips.
Unique ID can be put in OTP but there is no single specification for this.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds the pins for the board's USB Micro-B connector to the device
tree as zephyr_udc0, allowing USB examples to run natively on the board
Signed-off-by: James Anderson <jrsa@jrsa.co>
Adding support for the Adafruit QT PY RP2040.
Signed-off-by: Kelly Helmut Lord <helmut@helmutlord.com>
Signed-off-by: Ian Wakely <raveious.irw@gmail.com>
This commit updates the Ambiq Apollo4x series soc clock frequency
of defined instances to align with context of these dts files.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commit updates the support features in document and yaml files
of Ambiq apollo4p_evb and apollo4p_blue_kxr_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
