Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Update compatible strings and file names of Intel CPUs. Always use dash
instead of underscore. This will make all the compat strings and binding
files names for Intel consistent.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Two files ending with yml while the rest is ending with yaml, just
rename those two to avoid special handling.
Fixes documentation build.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable pin control support for SWO log backend, by creating a new
ITM node for the ARM instrumentation trace macrocell. Add pin control
properties under this node, and refactor the swo-req-freq property to be
defined within this node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The leon3 SoCs were missing definitions of the CPU node. This node is
now required for PM, so that power states can be defined.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This name should be the same as cpus node in dtsi. After the power
policy is added, the cpu-power-states in the CPU properties can
be used.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The Linux vendor prefixes list uses 'cdns'. Match it, especially since
we have that prefix in our own list as well.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Added file with common properties for cortex-m cores.
Added optional swo-ref-frequency property.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The only two supported operations for data caches in the cache framework
are currently arch_dcache_flush() and arch_dcache_invd().
This is quite restrictive because for some architectures we also want to
control i-cache and in general we want a finer control over what can be
flushed, invalidated or cleaned. To address these needs this patch
expands the set of operations that can be performed on data and
instruction caches, adding hooks for the operations on the whole cache,
a specific level or a specific address range.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is about it8xxx2 platform device tree.
Add driver's binding files, and one device tree as sample.
Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
Add power state property binding and include this property in cpu.
The pm-state attribute is a enum that matches with enum pm_state right
now the only timing attribute is the minimum residency that is the
minimum time for a power state be worthwhile.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In fixing up the altera vendor prefix, we forgot to rename the binding
files to match the compatible.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There are a few cases in which "altera" was used instead of "altr" as
the vendor prefix. Update DTS and bindings in those cases to use "altr"
Fixes#29373
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
