Driver init should be using instance based macros,
not nodelabels numbering, there is no guarantee
about which nodes will be assigned which instance numbers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add Kconfig guards for CONFIG_CAN_MAX_STD_ID_FILTER and
CONFIG_CAN_MAX_EXT_ID_FILTER as they only apply to the STM32 bxCAN driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove the STM32H7 specific Kconfig overrides for setting the maximum
number of standard and extended CAN RX filters as they are unused.
The number of available standard and extended filter elements for Bosch
M_CAN can be configured via the devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The SSD16xx driver used to use the SCREEN_INFO_DOUBLE_BUFFER flag to
indicate to the LVGL integration that it needs writes to be performed
twice. This was required because partial writes require both the old
and new buffer to be written.
This behavior is really an implementation detail and only applies to
partial refresh. Do this buffer maintenance in the driver instead.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Remove the optional call to ssd16xx_update_display() in
ssd16xx_clear_cntlr_mem(). This doesn't really belong in that function
and just adds a non-obvious boolean argument to the function.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Only UVB_EVT_REQUEST type passes the pkt argument.
This was overlooked in the last refactoring and
resulted in a zero pointer dereference.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
LSM6DSL's datasheet [1] lists 1666, 3332 and 6664 as valid ODR values for
accel and gyro. Update those from 1660, 3330 and 6660.
[1] http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Commit e015c00300 ("sensor: add lsm6dsl sensor driver") that introduced
initial support for lsm6dsl used 245dps instead of 250dps. According to
referenced documentation at [1] the latter is correct.
Use value of 250 instead of 245 for gyro range.
[1] http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This instance member is set as part of lsm6dsl_accel_set_odr_raw()
function, so there is no need to do it right before calling it.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Use the new dts properties for sampling time in the STM32 ADC driver:
- Get the sampling time from dts
- Remove all sampling time macro concatenation.
- Simplify/refactor setting of sampling time
- Check that sampling time is the same for all series using common channel
This also fixes a few cases where wrong sampling times were used for an
ADC instance (like ADC4 on U5, or ADC3 on STM32H723).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
If clock frequency was already high and a ahb prescaler greater than 1
was used frequency could temporary become higher than allowed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move definitions of the STM32 FDCAN specific registers to the front-end
driver implementation and implement remapping of these registers to/from
the standard Bosch M_CAN registers.
Some of the STM32 FDCAN register bit fields are limited in size compared to
the Bosch M_CAN specification. This is due to hardware limitations on the
number of elements in the various sections of the Message RAM. Add build
assertions to ensure the number of elements specified do not exceed the
hardware limitations instead of using custom definitions for these fields.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move definition of the NXP LPC MCAN specific Message RAM Base Address
register (MRBA) to the front-end driver implementation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some Bosch M_CAN IP core implementations use a fixed Message RAM
configuration, other use a fixed memory area and relative addressing,
others again have custom registers for configuring the Message RAM.
Move the responsibility for configuring the various Bosch M_CAN Message RAM
addresses to the front-end drivers. This removes some of the front-end
specific code from the backend. Provide a helper function for configuring
the most common variations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Expose the can_mcan_read_reg()/can_mcan_write_reg() along with all the
Bosch M_CAN register definitions for use in Bosch M_CAN driver front-ends.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Let the Bosch M_CAN front-end drivers supply their own register read/write
functions.
This is preparation for handling non-standard Bosch M_CAN register layouts
directly in the front-end and for accessing Bosch M_CAN IP cores over
peripheral busses.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use sys_read32()/sys_write32() instead of volatile struct for register
access. Be consistent in using unsigned constants in register
comparisons. Use locking around register read-modify-write operations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is a draft to support more controller implementations
with these drivers. The goal is also to make it easier to port
this driver to the new UDC API later.
We use compatible, like st,stm24f4-fsotg to support and enable
vendor-specific quirk. The core of the driver remains generic,
and therefore described and enabled by snps,dwc2 compatible.
STM32F4 support requires PINCTRL, even though pinctrl API is
generic, not all platforms implement it, so we have to include
and compile it conditionally.
Now we also switch to use new snps,dwc2 compatible and
explicitly force the controller into device mode,
as we do not support other roles or role changes.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add definition for GHWCFG1..4 registers to be able to obtain basic
information about PHY, endpoints, and Data FIFO.
Add GGPIO defines for STM32F4 SoC family USB controllers.
This implementation uses GGPIO to enable transceiver, VBUS
detection, and a few other functions.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Align and sort defines according to the position in memory.
Remove unnecessary parentheses.
Fix USB_DW_DSTS_ENUM_SPD_MASK.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Cleanup includes, fix build and missing kernel header include.
Move copyright notice to the top.
USB_DW_* macros are a bit misplaced in register header,
which is supposed to be about registers only.
USB_DW macro is used to point to base of controller register set.
Move it to driver code and add a new variable in driver's configuration
that takes the base address of the instance. This also makes later
porting to UDC API and support multiple instances easier.
Remove redundant DW_USB_IN_EP_NUM and DW_USB_OUT_EP_NUM
macros. Do not limit number of endpoint register in
struct usb_dw_in_ep_reg as it does not reflect common
register mapping of the controller.
Fix build warnings caused by USB_DW_EP_FIFO and use base variable
to calculate data FIFO access register.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
In the case that there is a situation where the controller
oscillator start-up timer doesn't expire, or the SPI can't
read the CLKRDY bit the driver would hang during init.
The config option ETH_ENC28J60_CLKRDY_INIT_WAIT_MS sets
the time that the driver will wait for OST before returning
an ETIMEDOUT error.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
According to the coding guidelines "dynamic allocation is not allowed".
This commit removes handling invalid DMA capable buffers by allocating
temporary buffer in a valid memory region, considering them as errors.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
I2C driver overwrites i2c_msgs buffers, which
causes statistics to fail counting.
This creates new variables to hold msg buffer information.
Fixes#57532
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Mutexs were added to improve the overlapping phenomenon
because there is a part that shares the i2c line.
Signed-off-by: yeongnam chu <yeongnam.chu@assaabloy.com>
Add a function to wait for the full (bulk) Nor-octoflah erase command.
When erasing the full octo-flash, the drivers waits until
the operation is ready and the external NOR mem becomes ready itself.
The full (bulk) erase operation lasts for several seconds.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Update KCONFIG for flash driver to depend on
DT_HAS_FIXED_PARTITIONS_ENABLED, since that is necessary for the
driver implementation
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add driver for OpenTitan SPI host.
Tested and verified single SPI full duplex on opentitan_earlgrey in
Verilator.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Add a semaphore to the entropy mcux caam driver
to make the driver thread safe, since some static
variables in the HAL can be the source of
some race conditions.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Rather than the rings, which weren't shared between userspace and kernel
space in Zephyr like they are in Linux with io_uring, use atomic mpsc
queues for submission and completion queues.
Most importantly this removes a potential head of line blocker in the
submission queue as the sqe would be held until a task is completed.
As additional bonuses this avoids some additional locks and restrictions
about what can be submitted and where. It also removes the need for
two executors as all chains/transactions are done concurrently.
Lastly this opens up the possibility for a common pool of sqe's to
allocate from potentially saving lots of memory.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Renamed CONFIG_ADC_GECKO to CONFIG_IADC_GECKO to eliminate confusion
between the Incremental ADC found on series 2 silabs gecko MCUs, and the
ADC found on earlier gecko series.
Signed-off-by: Jared Baumann <jared.baumann8@t-mobile.com>
Introduce a new SiP SVC subsystem to provide ARM Silicon Provider based
supervisory call services. SiP SVC service provides the capability to
send SMC/HVC call from kernel running at EL1 to hypervisor/
secure monitor firmware running at EL2/EL3 and also added SiP SVC shell
commands to exercise the service.
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Add driver for communicating with EL3/EL2 layer using smc/hvc call
for Silicon vendor Provided services for INTEL AGILEX SOC FPGA.
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Added device tree bindings and implementaion for setting the
spi controllers chip select setup and hold time settings.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The HAL function PWM_SetupPwm does the inverse division to get the
number of pulses from the frequency.
In the case of a prescaler of 1 and a period of UINT16_MAX cycles
this would result in an uint16_t overflow.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The LSM6DSO16IS is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSO16IS embeds a new ST category of processing,
ISPU (intelligent sensor processing unit) to support real-time applications
that rely on sensor data. The ISPU is an ultra-low-power, high-performance
programmable core which can execute signal processing and AI algorithms
in the edge.
https://www.st.com/en/mems-and-sensors/lsm6dso16is.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add STMEMSC_CTX I2C/SPI/I3C macros that can be reused among all STMEMSC
based ST sensor drivers to populate the stmdev_ctx_t stucture.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add test case for all drivers that are supporting the sensorhub
feature, and fix right away all the yet undiscovered issues.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In the real MiV platform, UART does not have any interrupts routed to
the interrupt controller.
Up to this stage, the driver implemented a separate thread to simulate
interrupt operation to enable shell samples. This is not required anymore,
as Zephyr can run shell on interrupt-less UARTs.
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Re-enable reception on the UART instance when `UART_RX_DISABLED`
triggers, which can happen when errors occur on the line.
This stops the driver permanently moving into an unresponsive state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The emulated espi and i2c bus controllers do not depend on CONFIG_EMUL
being enabled. When these fake bus controllers are enabled by their
assoicated compatible in the devicetree without CONFIG_EMUL it results in
linker failures for underlying peripheral emulators which may be difficult
to understand. The SPI config already depends on EMUL.
Make the ESPI and I2C emulated controllers depend on CONFIG_EMUL. Note:
This still allows linker failures if CONFIG_EMUL=n, but the linker failures
will be consistently at device driver instantiation due to a missing bus
controller. Regardless, this will be easier to debug when someone forgets
to enable CONFIG_EMUL.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
The nrfx SPI driver depends on semaphores, which require multithreading
support to be enabled.
Signed-off-by: Eivind Jølsgard <eivind.jolsgard@nordicsemi.no>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Use new nrfx hal function to memcpy from flash
instead of accessing the array directly.
That function is inlining a memcpy for real targets,
so there is no practical difference for those.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add charging mode support the PI3USB9201 emulator and add a backend API
for connecting/disconnecting a portable device partner.
Signed-off-by: Keith Short <keithshort@google.com>
Update the result callback routine to also provide information about the
charging mode role. This permits tests to validate plug/unplug events
detected by the BC1.2 device operating in charging mode.
Signed-off-by: Keith Short <keithshort@google.com>
This PR adds a driver for the BMI323, which implements
the following features:
* Enable and disable accelerometer and gyroscope respectively
* Set full scale for accelerometer and gyroscope respectively
* Set data rate for accelerometer and gyroscope respectively
* Get samples (x,y,z) from accelerometer and gyroscope respectively
* Get die temperature
* Set trigger to accelerometer data ready, and accelerometer any motion.
The driver implements device and device runtime power management. If
runtime management is used, it is initialized into the suspended state,
which soft-resets the device to achieve the lowest possible power
consumption, otherwise it is resumed when initialized. When resumed,
the bus is initialized, the feature engine is enabled, and INT1 is
initialized.
The driver only implements the SPI bus at this time. The driver is
prepared to be expanded with I2C support in the future.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Word size setting limited any SPI transaction to the frame
size. In addition to making the SPI inefficient this
broke drivers that set the word size. It appears that most
drivers use a one byte (8) size for this setting.
This change respects what I think is the intended use of
the word size setting. That is to set the length of
each element in a tx/rx buffer struct.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
Allow defining multiple instances of enc28j60.
Remove the ETH_ENC28J60_0 Kconfig option along with this.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add the `full-duplex` property for the `microchip,enc28j60` node.
Replace ETH_ENC28J60_0_FULL_DUPLEX Kconfig option with this property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This patch adds MULTITHREADING as a dependency to the nrfx i2c driver.
The driver uses semaphores internally and can result in linker errors
if MULTITHREADING is not enabled.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Updated the code to to invoke reset using PCR block
z_mchp_xec_pcr_periph_reset() instead of resetting
using I2C Configuration register
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Do not enable SOF event interrupt when the USB device driver is going to
discard the event anyway. This prevents completely unnecessary interrupt
handler from executing 1000 times a second when device is connected.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
nrfx 3.0 introduces parameter `_frequency` in
`NRFX_TIMER_DEFAULT_CONFIG()` macro. This patch aligns use of it.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Reworked QDEC SHIM to suppor multi-instance peripheral. Patch includes
Kconfig alignment for proper instance handling.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
New nrfx release extended nrfx_i2s API and requires to specify
pointer to driver instance structure. This commit aligns SHIM
to reworked nrfx driver.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
With new nrfx release SPIM driver stores frequency as a `uint32_t`
type representing frequency in `Hz` in its configuration structure.
Additionally `NRFX_SPIM_PIN_NOT_USED` has been removed,
`NRF_SPIM_PIN_NOT_CONNECTED` symbol is used instead.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
New nrfx release aligns PWM fields in driver instance structure
to common nrfx naming convention.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
New nrfx release replaces `nrf_wdt_behaviour_t` type
to `nrf_wdt_behaviour_mask_t` enumerator. As a result function
setting behaviour accepts `uint32_t` bitmask of behaviour.
This commit aligns symbols used in SHIM to the ones introduced
with the nrfx release.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
New nrfx release brings renamed macros and symbols in nrf_rtc.
This commit alligns RTC counter SHIM to it.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
New nrfx release brings change of Low frequency sources symbols
in nrf_clock hal to uppercase. This commit aligns all occurrences.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
When running cppcheck on eth_stm32_hal.c it generated a warning for
shiftTooManyBitsSigned.
The solution is to make sure that the numeric value shifted is unsigned.
Updated to use BIT() macro as suggested by GeorgeGCV.
Fixes: #57336
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Fix link error when both modems' drivers are enabled
as they both define the same structure but did not
make it static.
This fixes the CI build failure of
tests/drivers/build_all/modem/drivers.modem.simcom_sim7080.build
on particle_boron
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix the following build warning:
include <fcntl.h> without CONFIG_POSIX_API
is deprecated. Please use CONFIG_POSIX_API
or #include <zephyr/posix/fcntl.h>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add the ability for the flash simulator to store its contents in a
memory region.
This allows filesystems on the flash simulator to survive a reboot.
And allows subsystems (e.g. coredump) to store their info on ram while
using the (existing) flash partition backend.
Add a example (for nucleo_f411re) that shows how to configure the flash
simulator for hardware (cfg discussion #54166).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
Add support for a generic NTC, `ntc-thermistor-generic`. In this case,
the compensation table is provided via devicetree. Note that DT property
is prefixed with `zephyr,`, because while hardware related, it is linked
to a particular software implementation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactor driver to align a bit more with its Linux counterpart, ie,
ntc_thermistor. This driver did quite a few _unconventional_ things,
like using "zephyr," compatibles, a dedicated node for pre-computed
compensation table (referenced by the actual pseudo-device node), etc.
The comparison helper function should likely be simplified as well (to
avoid the need for custom wrapper for bsearch), but this can be done
later.
In this refactor, each thermistor gets a compatible, e.g. "epcos,xxxx".
Compatibles are known by the driver, so are compensation tables. This
simplifies devicetree files. There's no need to bother about
compensation tables in **every** board file if Zephyr supports a certain
NTC model.
In general we should respect Linux bindings, which in the end influence
how drivers are implemented. In this case, this principle resulted in
simplified, easier to use code.
For future developers, this is how support for a new NTC can be added:
1. Add to the end of the driver:
```c
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT vnd_model
static __unused const struct ntc_compensation comp_vnd_model[] = {
{ x, y },
...,
};
#define DT_INST_FOREACH_STATUS_OKAY_VARGS(NTC_THERMISTOR_DEV_INIT,
DT_DRV_COMPAT, comp_vnd_model)
```
3. In driver's Kconfig make sure it depends on
DT_HAS_$DT_DRV_COMPAT$_ENABLED
Note: $X$ means _value_ of X.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It looks like the Zephyr thermistor driver bindings were half-copied
from Linux ntc-thermistor. Zephyr principle is to maintain compatibility
with Linux, when possible, so there's no reason to deviate here. Convert
the connection type from a custom enum to a boolean, as Linux does.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This fixes this bug:
https://github.com/zephyrproject-rtos/zephyr/issues/57498
If bit 1 is set, then a write enable is required before
sending the 0xb7 instruction to enable the 4 byte address
mode, which this PR implements.
Signed-off-by: Frank Buss <fb@frank-buss.de>
1. Fix sensorhub names using the zephyr A.2 rule (use inclusive language).
The only exception is names within STMEMSC API and h/w register names.
2. Extend the STMEMSC API usage. It is always better to not code again
already existing functionalities.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Always set the interrupt pulse settings when sampling at greater than 4khz
to better ensure the interrupt line is toggled and caught correctly.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPI configuration did not set bit ordering or more importantly the clock
polarity which seemed to be misconfigured. Setting this corrects one more
quirk when working with this part on the TDK Robokit1
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Initial sensor driver for NPM1300 PMIC charger.
Includes basic configuration of charger voltage and current.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
The stm32_lptim_wait_ready() is waiting for the DIEROK flag
with a while loop. It should not be repeated.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When dma is enabled, spi_xmc4xxx_transcieve_dma() needs to disable the
isr used by spi_xmc4xxx_transceive(). Renable the isr at the
end of spi_xmc4xxx_transceive_dma() instead of in spi_xmc4xxx_transceive().
Doing this in latter function will fail compilation when interrupt
support is enabled but dma is disabled.
This is regression from 8494b6413a
but was only caught when xmc47_relax_kit was added which tested this
scenario in tests/drivers/spi/spi_loopback.
Fixes#57494
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Ignore touch events from GT911 IC when TOUCH_STATUS_MSK bit is not set
in status register. This resolves an error where the GT911 driver would
report a touch event end directly after a touch occured, as the touch
status register would be 0x0, which the driver incorrectly interpreted
as a touch release.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Commit f1b0b458b0 mistakenly selected the
SERIAL_SUPPORT_ASYNC kconfig for the kinetis uart
driver when enabling the lpuart driver. Revert this,
because the kinetis uart driver does not support async api.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
SPI / QSPI flash with density above 16MB must use 4 byte addressing mode
also on sector erase.
This patch selects the right addressing mode and opcode when 4 byte
addressing mode is selected
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Use level triggered interrupts instead of edge triggered interrupts to
make it impossible for the interrupt line to be active without the RX
thread attempting to read pending data.
This fixes a race condition for re-enabling the interrupt in edge
triggered mode, where `gpio_pin_interrupt_configure_dt` is not called
before the controller re-asserts the interrupt line.
As a result the controller can be reset before booting the RX thread.
Fixes#53980.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Some single-precision float constants were being compared against
double-precision floats. Make the constants doubles.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add Port 14/15 to device tree. These ports can only be configured as input.
Error out in gpio driver if user sets them as output.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Regenerate/rewrite the Bosch M_CAN register field definitions using the
GENMASK() and BIT() macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use the FIELD_PREP() and FIELD_GET() macros instead of manual bitshifts and
masking. Be consistent in the use of register field definition macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the local "const struct can_mcan_config *" variables from "cfg" to
"config" to be consistent with Zephyr conventions.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Get rid of the can_mcan_configure_timing() helper function as it provides
no benefit to just having the implementation split in can_mcan_set_timing()
and can_mcan_set_timing_data().
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the driver initialization function to the bottom of the file to be
consistent with Zephyr conventions.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Pass a pointer to the struct device for internal driver functions instead
of passing around a pointer to the register struct.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Reading the temperature calibration data requires disabling the icache
of the stm32h5x mcu.
Else a bus fault error occurs reading Address: 0x8fff8014-0x8fff818
Enable afterwards.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
When using gpio chip select the clock line seems to get stuck low after
some transactions. When attempting to use other SPI_CSR registers
the peripheral fails to work as expected.
Always using SPI_CSR[0] when using gpio chip selects resolves the issue.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch introduces support for NXP S32 CANEXCEL (CANXL) peripheral.
CAN protocol supporting:
- CAN classic
- CAN FD
Remote transmission request is not supported as this feature is not
available on NXP S32 CANXL HAL.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
These variables are now provided by the FindBabbleSim
cmake module, which finds them in the environment or thru
west.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In some cases, the enable pin may be already enabled by a previous
stage, e.g. bootloader. Therefore, it is not desirable to disable
the pin, as it could cause malfunctioning of the device. Refactor init
procedure so that we pick the right GPIO flags during the first
configuration stage.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some STM32 timers have more than one interrupt available.
When such timer is used it's likely that the first found interrupt
will not be the proper, 'cc' interrupt for input capture.
Existing implementation always connected the first irq, which worked
for timers with single, 'global' interrupt but broke input capture
for advanced timers with more interrupts.
Improve the IRQ connection logic by connecting the 'cc' interrupt
if it exists. Only if not found use the fallback mechanism of taking the
first index
Signed-off-by: Marek Metelski <marek@metelski.dev>
Add another helper function to send VW notification that is
neither a warning or conveys a system state.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Remove all enabling of CONFIG_EMUL_.* in favor of automatically enabling
peripheral emulators based on the compatible string presence in the device
tree and the one true CONFIG_EMUL.
Zephyr has long since moved to a model of enabling drivers based on the
presence of their associated IC's compatible string in the final devicetree
overlay. There is no reason that emulators can't align in just the same
way, and probably ought to to remove superfluous enabling of configs.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
According to the datasheet for Marvell PHY [1], the mode field of the
General Control Register 1 Page 18 occupies bits [2:0]. However, the macro
PHY_MRVL_MODE_CONFIG_MASK specifies the mask as 0x3, which would
correspond only to [1:0]. The code in phy_xlnx_gem_marvell_alaska_cfg()
uses the mask to set the mode field to 0 to set "RGMII (System mode) to
Copper" mode. Unfortunately, different chips have different reset values
(111 or 000) and in first case, the code would set the field to 100,
instead of 000.
Without this change, ethernet on Avnet MicroZed (Marvel Alaska 88E1512 PHY)
does not work.
Signed-off-by: Marek Vedral <vedrama5@fel.cvut.cz>
[1]: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf
If the boot loader already switched the system clock to PLL1 we need
to switch back to HSI first and disable PLL1 before we can configure
PLL1. Otherwise the register writes will simply be ignored and we'll
end up with an inconsistent state.
Most of the code has been recycled from `clock_stm32_ll_common.c`.
Signed-off-by: Sascha Silbe <sascha-pgp@se-silbe.de>
Signed-off-by: Sascha Silbe <sascha-pgp@silbe.org>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Code for power level property was accidentally
removed by accident from driver in commit 9921c59f40
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
spi_context_get_next_buf must not divide `len` by `dfs` because, in SPI,
buffer lengths are given in units of data (in this case, 16 bits), not in
bytes.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
By default HSIDIV is set to 0x01, so default frequency is 32 MHz.
This register should be always set based on dts value.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
The SAM GMAC driver is not able to use all of the receive buffers
concurrently. Frames larger than (buffer size) * (buffer count - 1) are
silently dropped. Fix it by adding one to MAIN_QUEUE_RX_DESC_COUNT.
Fixes#55701
Signed-off-by: Brandon Del Bel <delbel@umn.edu>
The `config` and `api` members of `struct device` are expected
to be `const`. This also improves reliability, as `config`
and `api` are stored in rom rather than ram, which has the
potential to be corrupted at runtime in the absense of an MMU.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
There are use cases for the pcie_ep driver where we don't
necessarily need the dma functionality. Added ifdef's around
the dma functionality so that it's only available if we
specify the dma engines in the device tree similar to
```
dmas = <&pl330 0>, <&pl330 1>;
dma-names = "txdma", "rxdma";
```
Signed-off-by: Tarun Karuturi <tkaruturi@meta.com>
Signed-off-by: Chris Friedt <cfriedt@meta.com>
This patch adds support for the TI INA3221 current monitor.
This is the datasheet used for reference:
https://www.ti.com/lit/gpn/ina3221
Since this device has three channels, there is a custom attribute to
select which channel is to be used when getting a sample.
Measurements are done on all enabled channels.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Make it possible to use CPOL/CPHA SPI clock modes with the SDHC driver.
Some cards require the clock to switch to low when not active.
Signed-off-by: Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
