nagendra modadugu 6b621a2939 dts: opentitan: update plic interrupt count to match spec ... previously `184`, update to `182`, per: https://opentitan.org/book/hw/top_earlgrey/ip_autogen/rv_plic/ Signed-off-by: nagendra modadugu <ngm@meta.com>		2024-03-22 09:23:46 +00:00
..
andes	dts/riscv/andes: add andestech,andescore-v5 compatible string	2024-01-31 10:41:49 +01:00
efinix	dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string	2024-01-31 10:41:49 +01:00
espressif/esp32c3	dts: bindings: can: remove optional sample point properties	2024-03-17 15:36:19 +01:00
gd	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
ite	it82xx2: Add missing ISRs for gpioj	2024-02-27 14:44:41 +01:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
nordic	dts: Remove support for nRF54H20 EngA	2024-03-18 19:11:36 +00:00
openisa	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
sifive	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
starfive	dts: riscv: starfive: add DT includes for JH7110 SOC	2024-03-13 11:39:51 -05:00
telink	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
neorv32.dtsi	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi	dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC	2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi	dts/riscv/litex: add litex,vexriscv-standard compatible string	2024-01-31 10:41:49 +01:00
virt.dtsi	dts/riscv: remove the timebase-frequency property	2024-01-31 10:41:49 +01:00