to make use of Espressif's hal in order to ease both
driver maintenance and code reuse between socs.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit adds support for Ethernet PHY drivers via a PHY API.
It also includes a driver for a generic MII compliant PHY
which supports most PHYs on the market.
Separating PHY driver from the SoC specific Ethernet driver
simplifies the Ethernet driver code and enables code re-use.
Drivers for specific PHYs with more advanced features, such as
RGMII delay in PHY can be developed independent of the Ethernet
MAC driver.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
This commit adds support for the Legend 2.5" boards (legend25_ssd and
legend25_hdd) based on the STM32F070CB MCU. These boards can be found in
the Seagate FireCuda Gaming Drive, Gaming Drive for Xbox, SSD Gaming
Drive for Xbox, and Gaming Drive for PlayStation devices. Both boards
contain the following hardware components:
- A B1414 LED strip connected to the PA7 pin (SPI MOSI)
- A SPI flash (FM25F005) connected on SPI2 bus
The Legend 2.5" HDD board also contains an activity LED connected on
TIM3 CH3
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
based on uart rom functions, also enable console driver
on top of this driver, which enables logging
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
We try to reduce the ambiguity between 'soc/nuvoton/' and
'soc/nuvoton_npcx' folders. Most if soc vendors name their soc folder by
the company name with SOC_FAMILY suffix instead of the company name
directly. It is clearer if the soc company has different product lines
that aim to specific markets.
In this CL, the 'numicro' suffix is used for Nuvoton Microcontroller
production line. It distinguishes the 'npcx' suffix that used for
Nuvoton Embedded Controller (EC) of Notebook PC product line.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The driver only support use case where the channels are used in mutual
exclusion.
Origin: Original
Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Add a shim that allows using the nrfx I2S driver via the Zephyr API.
Add also missing devicetree nodes representing the I2S peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-i2s" binding with a new property that allows
specifying the clock source to be used by the I2S peripheral (so that
it is possible to use HFXO for better accurracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
All the macro for dma-cells are now in the
include/drivers/dma/dma_stm32.h header file.
So the include/dt-bindings/dma/stm32_dma.h is no more
useful and removed from #include.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move @MulinChao, @WealianLiao, and myself from code owners entry
dts/arm/nuvoton/npcx to dts/arm/nuvoton.
So we will be chosen as reviewers automatically when dtsi files under
dts/arm/nuvoton are touched.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
A syscon device is a device managing a memory region containing a set of
registers that are not cohesive enough to represent as any specific type
of device. We need a driver for that because several other drivers could
use the same region at the same time and we need to io-map the region at
boot for MMU enabled platforms.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This patch add support for I2C on the Renesas R-Car.
This I2C hardware block can be found on various Renesas R-Car
SoC series.
It allows to perfom read and write on I2C buses in an
interrupt based way on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit adds a serial dummy driver compatible to vnd,serial.
This is needed that devices can access the uart device in tests
like tests/drivers/build_all/... .
Add myself as codeowner to avoid complicance check failure.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds the dts definitons for the seeed lora-e5 module.
Additionally I add myself as codeowner for the new dts/arm/seeed
directory.
This module packages a stm32wle5jc Sub-GHz Wireless Soc,
together with a 32MHz TCXO, a 32.768KHz crystal oscillator, and
power and RF circuitry.
With the introduction of lora support definitions for the radio
will be added in a future commit.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not enough time to review changes in these subsystems.
Propose to have VenkatKotakonda as KSCAN subsystem owner instead.
Adding SoC-specific driver owners.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add the code owner entries for all files related to the Xilinx GEM
Ethernet device driver.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
I cannot invest the time required for maintaining the networking
stack anymore, so I am stepping down from the maintainer role.
I am proposing Rober Lubos to be a new network maintainer.
I have been working with him for several years, and he is always
very helpful and knowledgeable to review and comment patches and
issues. He knows the network stack well and will for sure be able
to handle the task as he has been doing the maintenance already
for a long time.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Acked-by: Robert Lubos <robert.lubos@nordicsemi.no>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Convert the keyscan portion of the Holtek HT16K33 driver to adhere to
the kscan API instead of the GPIO API.
When this driver was introduced the kscan API was not present. The
keyscan driver was therefore implemented as a GPIO interrupt driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Adds @Thalley and @asbjornsabo (and the others
from the parent directory) to the babblesim audio
test directory.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This driver is for classic CAN, it makes use of CAN interface
in FIFO mode.
This driver support Standard ID as well as Extended ID.
Tested on H3ULCB, Ebisu platform, with external adapter and
in loopback mode.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Modify support for u-blox BMD-345-EVAL which uses the nRF52840
and a Skyworks RFX2411 FEM.
These edits follow the naming cnoventions that is used
with the other u-blox EVKs recently added, or in progress
This board is similar to the nRF52840dk_nrf52840 with the
addition of a FEM. Four Arduino GPIO pins have been
reassigned to the PA_LNA control pins.
u-blox would prefer to use this naming convention to match
other BMD-3xx-EVAL and EVK-NINA-Bx boards recently submitted.
Tested with blinky, button, and Bluetooth peripheral_hr
Checking dts files
Updated CODEOWNERS to rename bmd_345_eval to ubx_bmd345eval_nrf52840
Added CMakeLists.txt, updated board.c
Signed-off-by: Bob Recny <bob.recny@u-blox.com>
The cache API currently shipped in Zephyr is assuming that the cache
controller is always on-core thus managed at the arch level. This is not
always the case because many SoCs rely on external cache controllers as
a peripheral external to the core (for example PL310 cache controller
and the L2Cxxx family). In some cases you also want a single driver to
control a whole set of cache controllers.
Rework the cache code introducing support for external cache
controllers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch add support for polling based UART
on the Renesas R-Car SCIF (Serial Communication Interface
with FIFO)
This hardware block can be found on various Renesas R-Car
SoC series.
It allows to get console on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.
Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
- Move PM related APIs to `include/pm` so that it follows API `pm_`
prefix namespace. In order to make transition easier
`include/power/power.h` is kept pointing to `include/pm/pm.h`.
- Move most of device PM related content from `include/device.h` to
`include/pm/device.h` and `include/pm/runtime.h`.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds dictionary based logging support. Dictionary based
logging is binary based where one big difference is that
static strings are stored as pointers instead of the whole
string. This results in reduced space requirements for
storing log messages in certain scenairos.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).
INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move emul.h out of the top level include/ dir into
include/drivers/emul.h and deprecated the old location.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.
Controller can handle up to 32 GPIOs per banks.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add basic configuration for H3ULCB, just enough to see the
Zephyr boot banner on the ram console.
This configuration make use of the Cortex-R7 present on
r8a977951 SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add rak4631 board from RAKWireless based on nrf52840 and SX1262.
Board Documentation is completed
Signed-off-by: Guillaume Paquet <guillaume.paquet@smile.fr>
Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Armv8-R AArch64 MPU can support a maximum 16 memory regions, and the
actual region number can be retrieved from the system register(MPUIR)
during MPU initialization.
Current MPU driver only suppots EL1.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
According to Armv8-R64 Spec, MPU related meta data(region base/limit)
is 64 bits. So we need to re-define MPU related data structure here.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
It turns out that current known issues folder contains issues that are
no longer valid or present. I have searched for some of the regex
snippets listed but I have not been able to find any. Documentation was
the last active user of the known-issues folder, but has moved to
another solution.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move ptp_clock.h out of the top level include/ dir into
include/drivers/ptp_clock.h and deprecated the old location.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).
The support is based on the Cortex-M33 support that already exists in
Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add common SDMMC_LOG_LEVEL and SDMMC_VOLUME_NAME.
Initialize drivers at POST_KERNEL level.
Update CODEOWNERS after sdmmc drivers relocation.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add @evgeniy-paltsev as an ARC part owner in addition to
@abrodkin and @ruuddw, so he will be chosen as a reviewer
automatically.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
This patch includes initial support for FT800 display driver.
It includes basic features. It can be easily extended with more
FT800 display list and co-processor features.
Signed-off-by: Hubert Miś <hubert.mis@gmail.com>
I won't be supporting Zephyr for the foreseeable future, so remove my
association with specific subsystems.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Introduce PSoC-6 pinctrl infraestructure and definitions. This add
files to handle devicetree entries and following modifications:
- add pinctrl bindings
- update gpio bindings with pin-cells
- add pinctrl node and move gpio nodes inside
- declare pinctrl for current uart entries
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This new subsystem can be used to supervise individual threads. It
is based on a regularly updated kernel timer, whose ISR is never
actually called in regular system operation.
An existing hardware watchdog can be used as an optional fallback if
the task watchdog itself gets stuck.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add GPIO driver for QuickLogic EOS S3 SoC.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
I have not had time to work with USB recently, so removing myself from
MAINTAINERS and CODEOWNERS for the USB subsystem.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
In applications like logging the call site where arguments to
formatting are available may not be suitable for performing the
formatting, e.g. when the output operation can sleep. Add API that
supports capturing data that may be transient into a buffer that can
be saved, and API that then produces the output later using the
packaged arguments.
[ Documentation and commit log from Peter Bigot. ]
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add Thalley (emil.gydesen@nordicsemi.no) and asbjornsabo
(asbjorn.sabo@nordicsemi.no) as additional maintainers/codeowners for
bluetooth audio.
(Also adds empty audio.h file, that will later be expanded, so that
the include/bluetooth/audio directory now listed in CODEOWNERS
actually exists.)
Signed-off-by: Asbjørn Sæbø <asbjorn.sabo@nordicsemi.no>
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.
When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.
There are two kinds of problems with this choice:
1. PSCI is only defined for the non-secure world and it is designed to
boot CPU cores into non-secure state (that means that PSCI is only
supposed to work if Zephyr is running in non-secure state)
2. There can be other ways or standards used to start / stop a core
different from PSCI
This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.
For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add ability to build a UF2 (https://github.com/Microsoft/uf2)
image as an additional output type. This leverages the code
partition offset for the UF2 base address, and a configurable
UF2 family ID.
Includes an unmodified (except for headers for licensing, pylit
disabling) version of the uf2conv.py script copied the UF2
format specification repository, used to convert the bin to UF2.
Origin: UF2 file format specification reference utilies
License: MIT
URL: https://github.com/microsoft/uf2/blob/master/utils/uf2conv.py
commit: 587abb8b909266e9b468d6284f2fbd425235d1b5
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
We will need this to be able to DEVICE_DT_GET() bus devices from
tests/drivers/build_all in an upcoming commit.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit moves TFM CMakeLists.txt into Zephyr and relocates the
Kconfig.tfm file under the modules/tfm folder.
Updates the manifest to point to related TFM changes.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This patch implements a service that adds multiendpoint
capabilities to RPMsg. Multiple endpoints are intended to be used
when multiple modules need services from a remote processor. Each
module may register one or more RPMsg endpoints.
The implementation separates backend from the service, what
allows to extend this module to support other topologies like
Linux <-> Zephyr.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This script is essentially a Python rewrite of the CMake code we're
using to print boards in cmake/boards.cmake, plus some extra features.
Having this in Python will simplify some later adjustments to our
'usage' build system target in ways that will make its output easier
to read, while simultaneously making 'west boards' more useful.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This is a follow-up to commit 1c89837e79.
Update the path to dfu_usb.c after the file was moved, to prevent
compliance checks from failing because of non-existing file listed
in CODEOWNERS.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
I've been working on ESP WiFi drivers for some time now, so I would like
to help review new patches.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This reverts commit cabbd916cf.
This is considered to be useful enough that it should be restored
as a stable Zephyr API.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This adds a sample application for testing
the LiteX clock control driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
The SAM4L have a unique I2C driver. It shares simultaneously pins for
both master and slave controllers. Each controller have their own
instance. This introduces the TWIM controller that handles only the
master part.
The TWIM controller uses no copy and the driver was prepared to work
with both 7 and 10 bits address. The controller can handler up to 256
bytes for a single transfer allowing long data communication with
almost no CPU intervention.
The driver was wrote specifically to Zephyr. It receives a transfer
list of from upper layers to a specific device on the bus. It programs
the first and second transfer, if it exists, before start. At end of
full read/write interrupt, will program the next data block. This
process repeats until all transfers be executed. The driver uses
interrupt from TWIM to check for erros or program next tranfer.
Future work can enable low power mode on the driver allowing long
transfers with low power consumption.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This change adds support for DNS Service Discovery (DNS-SD)
as described in RFC 6763.
Fixes#29099
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Introduce TagoIO IoT Cloud HTTP post client example. This explorer
Zephyr network resources to demonstrate an end to end application.
The TagoIO allows that any user can test on a easy way Ethernet, WIFI
and Modem (PPP) with BSD sockets. The example provides overlays to
configure WIFI and Modem.
The application consists an a pseudo temperature sensor that sends
periodically data to TagoIO IoT Cloud platform. The data can be
visualized on a web browser dashboard, cellphone or tablet. The
steps to configure TagoIO are described on the example documentation.
Special Variables:
- CONFIG_TAGOIO_DEVICE_TOKEN DEVID token generated by TagoIO
- CONFIG_TAGOIO_HTTP_WIFI_SSID SSID when using WIFI
- CONFIG_TAGOIO_HTTP_WIFI_PSK PASSWD when using WIFI
- CONFIG_MODEM_GSM_UART_NAME UART label when using MODEM
- CONFIG_MODEM_GSM_APN APN when using MODEM
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Inventek es-WIFI modules shield. This shield exposes es-WIFI driver
using Arduino Uno R3 header by UART or SPI interfaces. It shows how
user can create their own overlay and expose es-WIFI driver.
The current Inventek's EVB doesn't have all pins necessary to control
the module by Arduino hearder. This shows how to wire to get ISM43xx
EVB working.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add uart bus interface to extended esWIFI driver. This enables all
Inventek modules with IWIN AT Commands firmware.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This change reworks the cc13xx_cc26xx IEEE 802.15.4 driver to use
the TI RF driver API that is available in modules/hal/ti.
There are a number of benefits to using TI's API including
- a stable multi-OS vendor library and API
- API compatibility with the rest of the SimpleLink SDK and SoC family
- potential multi-protocol & multi-client radio operation
(e.g. both 15.4 and BLE)
- coexistence support with other chipsets via gpio
- vetted TI RF driver resources, such as
- the radio command queue
- highly tuned / coupled RTC & RAT (RAdio Timer) API
Fixes#26312
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
This provides structure for the regulator device hierarchy and a
driver for GPIO-controlled regulators along with its binding.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Adding myself @jenmwms and @aasthagr as codeowners for
/arch/x86/, /soc/x86/, /boards/x86/, and
/drivers/serial/*ns16550* for x86 development.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Move the devicetree bindings for Analog-to-Digital Converters (ADCs)
from dts/bindings/iio/adc to dts/bindings/adc as Zephyr does not have
an IIO layer.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
In early Zephyr days, STM32 code base greatly benefited from the care
of a handful of people.
These days are gone and so did these few people that haven't been
contributing for at least a year now.
CODEOWNERS file is updated to reflect current status of contribution,
for the areas where the is an active contributor.
Let them be thank for these initial contributions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add timing functions and APIs. This is now used with some of the tests
we have for performance and metrics and will be used whereever timing
informations are needed, for example for tracing, profiling and other
operations where timing info is critical.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a generic host command handler framework that allows users to
declare new host command handlers with the HOST_COMMAND_HANDLER macro
at build time. The framework will handle incoming messages from the
host command peripheral device and forwards the incoming data to the
appropriate host command handler, which is looked up by id.
The framework will also send the response from the handler back to the
host command peripheral device. The device handles sending the data on
the physical bus.
This type of host command communication is typically done on an embedded
controller for a notebook or computer. The host would be the main
application processor (aka AP, CPU, SoC).
Signed-off-by: Jett Rink <jettrink@google.com>
The host command peripheral device API abstracts how an embedded
controller sends and receives data from a host on a bus. Each bus like
eSPI, SPI, or I2C would implement their own host command peripheral
device. Each hardware device would then handle the necessary hardware
access to send and receive data over that bus.
The chosen host command peripheral device will be used by the host
command handler framework to send and receive host data correctly.
Signed-off-by: Jett Rink <jettrink@google.com>
@ulfalizer hasn't been active for several months, remove him and add
@mbolivar-nordic. We can add @ulfalizer back if he comes back to the
project.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
At present this test uses an EEPROM emulator. Reuse the same test to
also use the real Atmel AT2x driver and an AT24 emulator, via the I2C
emulation controller.
EEPROM reads and writes for eeprom1 go through the AT2x driver, which
converts them to I2C transactions, which are passed through to the
AT24 emulator for processing. This approach makes more use of 'real'
code, in this case the Atmel AT2x driver.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an emulation controller which routes I2C traffic to attached
emulators depending on the I2C address selected. This allows drivers
for I2C peripherals to be tested on systems that don't have that
peripheral attached, with the emulator handling the I2C traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Create a header file and implementation for emulators. Set up a linker
list so that emulators can be found and initialised at start-up.
Emulators are used to emulate hardware devices, to support testing of
various subsystems. For example, it is possible to write an emulator
for an I2C compass such that it appears on the I2C bus and can be used
just like a real hardware device.
Emulators often implement special features for testing. For example a
compass may support returning bogus data if the I2C bus speed is too
high, or may return invalid measurements if calibration has not yet
been completed. This allows for testing that high-level code can
handle these situations correctly. Test coverage can therefore
approach 100% if all failure conditions are emulated.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Simon Glass <sjg@chromium.org>
The FaZe board can be found in the Seagate FireCuda Gaming SSD devices.
A NVMe SSD and two chips are embedded: an ASMedia ASM2364 USB-to-PCIe
bridge controller and a NXP LPC11U67 MCU. The former is handling the USB
type-C to SSD I/Os while the latter is dedicated to the LED effects. The
two chips are connected together through I2C and GPIOs.
This Zephyr port is running on the LPC11U67 MCU.
Here is a list of the devices connected to the LPC11U67 on a FaZe board:
- ASMedia ASM2364 USB-to-PCIe bridge (I2C master on port O)
- 6 RGB LEDs connected connected to a TI LP5030 LED controller
(I2C device on port 1)
- 1 white LED (SSD activity blinking)
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This adds a very primitive coredump mechanism under subsys/debug
where during fatal error, register and memory content can be
dumped to coredump backend. One such backend utilizing log
module for output is included. Once the coredump log is converted
to a binary file, it can be used with the ELF output file as
inputs to an overly simplified implementation of a GDB server.
This GDB server can be attached via the target remote command of
GDB and will be serving register and memory content. This allows
using GDB to examine stack and memory where the fatal error
occurred.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Sort entries alphabetically and cleanup top level menu for each
subsystem. Move stats subsystem Kconfig from debug into its own Kconfig.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.
This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add myself (@cbsiddharth) as code owner for subsys/mgmt/osdp/,
samples/sybsys/mgmt/osdp/ and includes/mgmt/osdp.h.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
Zephyr introduced subsys/mgmt folder for MCU management. Move UpdateHub
sample to its correspondent folder at sample/subsys/mgmt folder.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Zephyr introduced subsys/mgmt folder for MCU management. Move UpdateHub
to this newly and dedicated space.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
In order to be able to add more entries under 'subsys/mgmt', move the
current contents of it, which relate exclusively to MCUMgr, to its own
folder.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add @abrodkin to the list of CODEOWNERS for ARC code (ARCH,
BOARDS, DTS) instead of @vonhust.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add an entry in CODEOWNERS for auto-assigning reviewers
in MAINTAINERS.yml and get_maintainer.py files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
The esp_8266 shield was added without owner on #24710. Add myself as
an owner of esp_8266 shield files.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The Atmel RF2xx module shield is a generic solution to enable any Atmel
AT86RF2xx IEEE 802.15.4 transceiver. This module enables IEEE 802.15.4
RF2xx Zephyr driver.
The Atmel RF2xx module shield enables any board with an Atmel Xplained,
Xplained-Pro, Arduino or MikroBus expansion header to connect to
networks operation with IEEE 802.15.4, OpenThread or any other stack
based on this media type.
The Atmel RF2xx module is configured to allow interoperate with other
medias like Ethernet. User need configure network stack properlly.
Fixes#26259.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Add setup to utilize buildkite for CI purposes:
1. .buildkite/hooks/pre-command:
* Handles getting git checkout setup against upstream repo
* Setup some west module cache (dirs, clean out files & locks)
* init dir for ccache
2. .buildkite/hooks/post-command:
* Report disk usage (meant for possible debugging)
3. .buildkite/pipeline.yml [uses to determine what to do]:
* setup zephyr env vars
* set which docker container to use
(export some local disk caches for git, west modules, and ccache)
* uses plug to general build annotation on failure (junit-annotate)
4. .buildkite/run.sh [ buildkite wrapper to invoke scripts/ci/run.sh ]
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This change enables specific compiler and linker options to be used in
the case that an arch/posix/os.arch.cmake file exists.
Note: os and arch in the above case are evaluations of
CMAKE_HOST_SYSTEM_NAME and CMAKE_HOST_SYSTEM_PROCESSOR.
Otherwise, the existing "generic" compiler and linker flags in
arch/posix/CMakeLists.txt are used.
Additional flags and checks are provided in
arch/posix/Linux.aarch64.cmake.
Added scripts/user_wordsize.py to detect if userspace is 64-bit or
32-bit, which should be consistent with the value of CONFIG_64BIT
for Aarch64 on Linux.
Fixes#24842
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Add a disk access driver for the stm32 sdmmc component. The driver is
based around the stm32 cube HAL and uses the blocking API.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Many chips have only one serial port. When the serial port is occupied
by other devices, there is a lack of a console to output debugging
information. Semihosting can provide a console. The disadvantage of
semihosting is that a debugger must be connected, so it can only be
used for online debugging.
Signed-off-by: ZhongYao Luo <LuoZhongYao@gmail.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Cloned from counter_basic_api with modifications based on DS3231
limitations:
* Only one device tested per board;
* Counter cannot be stopped or started;
* Alarms are serviced by worker thread, so are not invoked from ISR
and require that test thread yield to allow processing (no
k_busy_wait());
* Multiple Alarms test is disabled as documented in test.
Additional tests were added for DS3231-specific API.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.
The basic functionality is exposed as a counter that is always running
at 1 Hz. Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock. This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This commit renames the CAN sample directory name from `CAN` to `can`
to be consistent with others.
Noting that the CAN driver test directory is named `tests/drivers/can`,
we have no excuse for naming the CAN driver sample directory
`samples/drivers/CAN`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
DAC (digital to analog converter) peripheral driver with a generic API
suitable for most MCUs (only basic DAC features considered).
Signed-off-by: Martin Jäger <martin@libre.solar>
Add pinctl support for the SAM UART and SAM USART devices. We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
