pm_device_runtime_get() must be called after pd_intel_adsp_init() is
called for each device, because the latter calls
pm_device_runtime_enable(), which sets the device runtime PM use
count to 0. The current wrong calling order causes a DSP panic
because of an unbalanced pm_device_runtime_put(). Fix this by
delaying pm_device_runtime_get() until the POST_KERNEL initialisation
step.
Fixes commit c3a6274bf5 ("intel_adsp: ace: power: Prevent HST
domain power gating")
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Now that:
1 - LS Clocks sources values are identical accross series
2 - We're able to extract this value from device tree
define STM32_LPTIM_CLOCK choice symbol from device tree
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
For a CLIC the vector table has to be aligned by 512 bytes, if there are
between 65 and 128 interrupts, which is the case for the gd32vf103.
`isr_wrapper` has to be aligned to 64 bytes, s.t. the lower 6 bits of
mtvec are 0.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
For a proper initialisation, the soc-specific `__nuclei_start` has to
be executed before the common `__start`. To ensure that `__nuclei_start`
is linked first, I added the linker section init.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
A lot of the entry.S is again implemented in common/vector.S.
I removed everything redundant and changed the jump to the common
symbol __start at the end.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
.bss and .data are uncached in Zephyr builds for intel_adsp. No need
to try to manipulate cache of objects in those sections.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The MCAUSE register has the "Interrupt" flag defined defined at XLEN-1
position (31 for 32-bit, 63 for 64-bit). This is not an SoC specific
option, and there's no need to expose it publicly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Commit 447a492 switched to `sys_cache*` to enable caches at SoC init. To
preserve the old behavior of enabling caches at init, is missing to
select `CONFIG_CACHE_MANAGEMENT`.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since d992683db5 (soc: arm: replace redundant config option for
caches for nxp_imx), RT1xxx series will not have cache enabled at boot
unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance,
enable CONFIG_CACHE_MANAGEMENT by default.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.
The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the redundant cache config options for kv5x and use
the sys_cache* functions to enable the caches. This will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache* for enabling the caches in nxp_s32. This automatically
considers CONFIG_CACHE_MANAGEMENT and will activate the
cases only if this is active.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This option is no longer needed, all SoCs have been moved out from
soc/riscv/riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganized as follows:
- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)
Also moved out of riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.
[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
fpga-and-soc-design-tools/mi-v
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganize following the hierarchy found in the vendor website [1]:
- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518
Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].
[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
B91_Generic_Starter_Kit_Hardware_Guide/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When Power Management is enabled (CONFIG_PM=y),
the CONFIG_IDLE_STACK_SIZE of 320 is not enough :
Increase its size to 512.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The defconfig.series file for the stm32f4 incorrectly redefines
the PM Kconfig in order to select two dependencies, COUNTER and
COUNTER_RTC_STM32_SUBSECONDS, instead of setting a default for
them if PM is included.
This commit fixes the error described above.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Currently SOF has disabled CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE option and
use pm_suspend_devices() to suspend and resume IPC device during D3
power flow. The pm_suspend_devices() function skips suspending devices
that are busy. In very rare cases, the IPC device is busy during the
power state transition, which results in the device not being restored
during reboot. This happens when FW sends a message to the HOST and
waits for ACK, and the HOST simultaneously sends a SET_DX message to the
DSP. This suspend/resume logic in IPC driver does not work well when the
system enters the D3 state because it is not a suspend state, but rather
a power-off. IPC does not require suspending, only reinitialization when
exiting D3. We cannot avoid this one missing ACK and it cannot block the
DSP from turning off.
When FW receives a SET_DX message it checks whether it can enter the D3
state and then returns an error (via IPC) or calls the pm_state_force
function. Success response is sent directly from power_down assembly and
not via ipc driver. This is because after receiving the response, the
HOST will turn off the DSP.
In order for the transition to D3 to take place, only the primary core
can be active, all pipes must be stopped (and therefore all modules in
FW). The only active thread at this time is the Idle thread. Driver on
the host will not send another ipc because is still waiting for
response. FW can try to send only two notification:
- FW exception: from this place there is no return to continue the power
transition,
- log buffer status: skipped, they remain in the queue without being
sent.
I'm moving pm_device_busy_clear(dev) from IRQ handler to
intel_adsp_ipc_send_message function so the pending ACK does not block
power transition.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
HDA DMA driver uses an excessive value of 128 bytes as required alignment
for DMA buffer size. This may result in the correct buffer size (e.g.
32-byte aligned, which is DT-compliant) being silently truncated before
writing it into DGBS register. This patch changes the requirement to the
value implied by DGBS register format (effectively reduces to 16 bytes).
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
The previous implementation of the sys_arch_reboot function
for the Atmel SAM series was using NVIC_SystemReset.
This caused a reboot time of around 20 seconds on a SAM4SA16CA,
which is now reduced by directly writing to the
reset controller control register (RSTC_CR).
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
QEMU MMU tracing showed that there might be something wrong with
its Xtensa MMU implementation, which result in access violation
when running samples/userspace/hello_world_user.
Here is the MMU trace from QEMU from failed runs:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00103050, ret = 26
The place where it fails is during reading from 0x109014.
From the trace above, the auto-refill maps 0x109000 correctly
with ring 0 and RW access with WB cache (which should be correct
the first time under kernel mode). The page 0x109000 is the libc
partition which needs to be accessible from user thread.
However, when accessing that page, the returned physical address
became 0x103050 (and resulting in load/store access violation).
We always identity map memory pages so it should never return
a different physical address.
After forcing TLB invalidation during page table swaps, the MMU
trace is:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
get_pte: autorefill(00109028): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109028): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
get_pte: autorefill(00109014): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109014): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00109014, ret = 0
xtensa_cpu_tlb_fill(00109020, 0, 0) -> 00109020, ret = 0
Here, when the same page is accessed, it got the correct PTE
entry, which is ring 2 with RW access mode (but no cache).
Actually accessing the variable via virtual address returns
the correct physical address: 0x109014.
So workaround that by forcing TLB invalidation during page swap.
Fixes#66029
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need for this config here and it is messing
with total sys heap calculation.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Supporting Stop1 mode while BLE RF is enabled requires some specific
adaptation and usage of STM32WBA Cube BLE controller scm API.
scm (Secure clock manager) is in charge of switching clock depending
on RF status and should be informed of PM stop modes scheduling.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32WBA controller uses a PKA driver to perform cyphering operations
on keys. Since PKA hardware block requires RNG clock to be enabled, a
synchronization with zephyr RNG driver is needed.
Use RNG enable status to check if RNG could be switched off or needs to
be switched on.
Similarly in entropy driver, don't cut RNG clock if PKA is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The DC233C core has support for both i-cache and d-cache.
So mark it as such so we can test caching of Xtensa in QEMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Definition of ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT,
which is used in the intel_adsp_force_dmi_l0_state function,
is missing.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
Currently on zephyr, RAIL library is used only by Bluetooth applications,
with this update, it will be able to be used for sample applications
for custom radio phys.
All files were copied from Silicon Labs GSDK v4.2.4.
Signed-off-by: Zoltan Havas <zoltan.havas@silabs.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Separating two new functions force and allow l1
to have the current state with separated functions
in the ipc file so that SOF can call these
functions via IPC DMI_FORCE_L1_EXIT. Change related
to the addition of a new parameter to force
DMI L1 exit on IPC request.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This follows the idea to remove any z_ prefix. Since MMU has
a large number of these, separate out these changes into one
commit to ease review effort.
Since these are no longer have z_, these need proper doxygen
doc. So add them too.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Use the already available in the tree mechanism of adding assembly
instructions right after WFI/WFE to implement the workaround for
nRF5340 anomaly 168 (replace the 4 NOP solution used on the network
core as it turned out to be insufficient) and provide two related
Kconfig options so that users are able to adjust the workaround to
their actual needs (disable it entirely or use it in the extended
version).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Enable the TF-M NS storage partition for nordic boards.
This partition is otherwise not used, and configured as secure.
Fixes: #59376
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the Kconfig for the npcx eSPI driver so it's automatically
enabled if the devicetree node is enabled.
Signed-off-by: Keith Short <keithshort@google.com>
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.
While we're at at: remove commented out code
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
GCLK Gen 2 was dedicated to USB, but never setup... this patch
configures it for 48 MHz, derrived from DFLL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.
Fixes#66147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This changes remove extraneous includes causing issues with cycles in
includes subsequently having code requiring definitions from CMSIS
while it’s configuration hasn’t completed yet.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Kconfig parameters, header’s default & silicon vendor’s SDK configuration
for CMSIS Core, must be consistent. Depending on the inclusion order of
the headers, this is currently not always the case.
This change introduces consistency checks & enusers defaults match their
Kconfig settings.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is a part of introduction of new WTD instances.
It adds new Kconfig symbols that can be used in WDT shim and
nrfx driver.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
In an earlier commit, the riscv-privileged level implementation of
`arch_cpu_idle()` is not included unless `CONFIG_RISCV_HAS_CPU_IDLE` is
enabled.
This commit ensures the option is enabled on all the existing CPUs, thereby
maintaining the existing behavior.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
The current configuration comes with a common implementation of
`arch_cpu_idle()` for the whole riscv-privileged family, utilizing the
`WFI` instruction to place the CPU into a light sleep state, with the
assumption that it will be awakened later by interrupts such as SYSTICK.
However, this approach is not always effective, particularly in scenarios
where the SYSTICK is not a valid wake source.
This commit uses `CONFIG_RISCV_HAS_CPU_IDLE` as the build condition of the
family-level `idle.c`, allowing CPUs that do not enable this option to
fallback to a generic arch-level implementation in
`arch/riscv/core/cpu_idle.c`.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Change makes EGU instance used for anomaly 109 workaround configurable.
The default EGU instance (5) may be used for other purpose.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.
Fixes#65634
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There are symbols are both defined by the NXP S32 HAL and
the CMSIS RTOS V2 wrapper, to avoid interference between
them, redefine the symbols under an enum.
Also this is may a common issue for all NXP S32 platforms,
move to common place to be reused
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.
This SoC has a dual core lockstep Cortex-R52 CPU.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.
While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.
We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.
Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.
This imply to add a pfc_base parameter to most of the pfc_rcar
function.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The original SHI module only has one output FIFO buffer. It costs a lot
when the driver has to send/change the protocol control code because it
must fill out all 128 bytes of output FIFO. In npcx4, we introduce
another output buffer in 1-byte depth. These two buffers can switch back
and forth during the transaction. We can use the single-byte buffer
to send the control code and the 128-byte FIFO to send the data payload.
It helps improve the SHI driver's efficiency.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Secondary dsp is idle and waiting for interrupt before it is totally
halted. The other active cores can trigger idc interrupt to this core,
this can wake it up and result to fw panic. Mask idc interrupt as timer
interrupt to prevent this case.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Annotate posix_exit() and nsi_exit() as noreturn
mainly to ease the life of static analysis tools.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Andy Ross re-implementation of MMU layer with some subtle changes,
like re-using existent macros, fix page table cache property when
direct mapping it in TLB.
From Andy's original commit message:
This is a reworked MMU layer, sitting cleanly below the page table
handling in the OS. Notable differences from the original work:
+ Significantly smaller code and simpler API (just three functions to
be called from the OS/userspace/ptable layer).
+ Big README-MMU document containing my learnings over the process, so
hopefully fewer people need to go through this in the future.
+ No TLB flushing needed. Clean separation of ASIDs, just requires
that the upper levels match the ASID to the L1 page table page
consistently.
+ Vector mapping is done with a 4k page and not a 4M page, leading to
much more flexibility with hardware memory layout. The original
scheme required that the 4M region containing vecbase be mapped
virtually to a location other than the hardware address, which makes
confusing linkage with call0 and difficult initialization
constraints where the exception vectors run at different addresses
before and after MMU setup (effectively forcing them to be PIC
code).
+ More provably correct initialization, all MMU changes happen in a
single asm block with no memory accesses which would generate a
refill.
Signed-off-by: Andy Ross <andyross@google.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
