The x-nucleo-iks01a3 shield is equipped with a DIL24 socket where
different compatible sensors may fit. This commit add support to
lis2de12 on DIL24 in such a way that, if sensor is not present, test
would just skip it and proceed. Other sensors may be added in future.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2de12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add APIs to:
1. read/write sensor regs on i2c/spi bus enabling adrress
auto-increment in a stmemsc specific way.
2. read/write sensor custom APIs.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
uicr_ranges dictionary entries did not contain the `_FAMILY` suffix, now
used by self.family variable, resulting in an always false check.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
1. Support the dma mode for andes_atcspi200
and use board adp_xc7k_ae350 for testing.
2. Refine the function mechanism.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Remove the redundant code.
2. Use sys_set_bits and sys_clear_bits instead of customized MACRO.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
remove pci bus compatible id dependency from qemu platforms overlay
files for disk and ivshmem test apps. This already provided as part of
respecitve board dts files and hence no need to duplicate here.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
add resource enumeration and acpi method shell commands such as
retrieve mmio and interrupt resources.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
add interface for encode irq flags from acpica to arch specfic.
Currently enabled only for x86 archiecture.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
add a separate timer interface for acpica lib instead of using
system timer which might use driver interface such as HPET and this
might cause init priority issue if a driver which need to init
before system timer driver instantiate.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This commit introduces a new IPv6 API for positive reachability
confirmation, as specified in RFC 4861, Section 7.3.1. This feature aims
to enhance the effectiveness of the Neighbor Discovery mechanism, by
enabling upper-layer protocols to signal that the connection makes a
"forward progress".
The implementation within TCP serves as a reference. Compliance with
RFC 4861, especially Appendix E.1, was ensured by focusing on reliable
handshake and acknowledgment of new data transmissions.
Though initially integrated with TCP, the API is designed for broader
applicability. For example, it might be used by some UDP-based protocols
that can indicate two-way communication progress.
Signed-off-by: Łukasz Duda <lukasz.duda@nordicsemi.no>
Add a new #nordic,ficr-cells property, so that we can specify a FICR
offset in a phandle-array, e.g.
nordic,ficrs = <&ficr 0xff>;
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
gcovr 7.0 has some incompatible format, stick with 6.0 for now until we
have a compatible solution with gcovr 7.0 output.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We cannot always start the service monitor thread statically
because the static threads are started after the application
level. This means that when config library wants to start
dhcpv4 server which uses socket services, there would be a
deadlock. Simplest solution is to start the service thread
directly from socket service init function.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Not only check if the address pool belongs to the same subnet as the
server, but also that it does not overlap with the server address -
otherwise the server might end up assigning its own address.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
We need to enable this configuration for all R-Car ARM64 boards.
First and foremost, we definitely should run Zephyr on the boards
in the NS-EL1 state. The EL3 is used for TF-A, EL2 is used for
U-Boot, and Xen in the case when we run Zephyr as Dom-0. The S-EL1
is used for OP-Tee, and S-EL0 is used for OP-Tee apps.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
When the CIS of a source ASE disconnects, the server shall put
it into the QoS Configured state, which is not really part of the
state machine for source ASEs, but more like a hidden bonus state
change.
The state machine handler in the unicast client has been updated
to support this state change.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
On the Polarfire SOC Icicle Kit the SPI pins are routed to MikroBus.
Enable SPI by default.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Add driver for the Microchip Polarfire SOC MSS SPI controller.
The interrupts of the MSS SPI are routed through PLIC(Platform level
interrupt controller).
Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Implement tests for `sched_setparam()` and `sched_setscheduler()` .
Both functions are actually placeholders and just return `ENOSYS`
since Zephyr does not yet support processes or process scheduling.
signed-off-by: Gaetan Perrot <gaetanperrotpro@gmail.com>
Implement `sched_setparam()` and `sched_setscheduler()` POSIX APIs
as a part of PSE53 `_POSIX_PRIORITY_SCHEDULING` option group.
Both functions are actually placeholders and just return `ENOSYS`
since Zephyr does not yet support processes or process scheduling.
signed-off-by: Gaetan Perrot <gaetanperrotpro@gmail.com>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.
As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
the device tree offers a default config (qdec0) for 1x qdec at TC0,
however does not offer a default config for qdec1 - qdec3.
this will be added with this commit. Fixes#65610
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
This update fixes the qdec in SAME70b, which could not be compiled prior to
this fix, due to missing TC_CMR definitions. Moreover it fixes#65432.
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
