Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add driver for ScioSense ENS160 multi-gas sensor. The driver includes
support for I2C and SPI, attributes for setting temperature and
humidity compensation and data ready trigger.
Also add ScioSense to the list of vendor prefixes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add clarifications to mipi-dbi bindings to avoid the confusion
between two options, write-only and duplex.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Unlike SPI nodes, I2C nodes (i2c20, i2c21, i2c22 and i2c30) did not have
this required property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove pinctrl from device tree since it is not required
when internal oscillator is used.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add FlexSPI clock source to RT1010 devicetree definition for FlexSPI
node, to match FlexSPI clock source defined on standard FlexSPI dt node
that is removed in the RT1010 devicetree.
Fixes#68488
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
... so that there is no need to include that header individually
for every added board based on an nRF SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... so that it can be included by ARM and RISC-V cores. For the same
reason, SysTick can no longer be disabled in this common file.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor. The size Property becomes useless.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor. The size Property becomes useless
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Setup rx-clock-source for XIP flash. When running from RAM, the FLEXSPI2
attached SIP flash will be reconfigured, so we must ensure the
configuration used for it is valid.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2de12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Add a new #nordic,ficr-cells property, so that we can specify a FICR
offset in a phandle-array, e.g.
nordic,ficrs = <&ficr 0xff>;
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.
As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/adc and arm.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/bluetooth, can, dac and display.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/net, power-domain, pwm and qspi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/retained_mem, rng, serial and spi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/timer, usb-c, usb and watchdog.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/pinctrl directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/dma directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/sensor directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/clock directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Create a folder for RZ Renesas range device tree to follow how it's
done for other renesas ranges.
It will also help to better delimit areas to maintain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Provide jtag port pins description, so they can be used to be set in
analog mode when not required to save power (around 40uA saved in total).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In some hardware designs it might happen that the reset signal
for the TLE9104 is not used only for this purpose, but instead for
instance to reset other devices at the same time. For such a hardware
design it is then necessary to make the reset GPIO optional. The reset
will have to be triggered earlier on.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This implements the daisy chain feature of the low side switch
BD8LB600FS. The daisy chaining is in hardware achieved via
connecting the MISO and MOSI lines of multiple instances of the IC
in a row. It is implemented in the driver through a variable number
of GPIOs on one instance. Therefore, one device tree instance of the
IC will handle multiple daisy chained physical instances.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds source and header files required for bmp581 I2C driver.
I have used bmp581_user.h to add more usage related definitions
but bmp581.h to add hardware related definitions.
Signed-off-by: Talha Can Havadar <havadartalha@gmail.com>
Signed-off-by: Gerhard Jörges <joerges@metratec.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
Many sensors have multiple functions, for example, icm42688 supports
accel, gyro and temperature, and the sensor streaming api always mixes
the multiple functions in one function call. So we need add a layer in
sensing subsystem to dispatch the result returned from sensor streaming
api for each function.
I changed the sensor-type(int) to sensor-types(array) in sensing sensor
device bindings, so that one device can map to multiple instances of
sensing sensor.
Signed-off-by: Zhang Lixu <lixu.zhang@intel.com>
Add hinge angle virtual sensor for sensing subsystem, hinge angle sensor
takes both base accel and lid accel as reporter.
Signed-off-by: Zhang Lixu <lixu.zhang@intel.com>
This commit introduces a driver for NXP's eDMA IP.
The main reasons for introducing a new driver are the following:
1) The HAL EDMA wrappers don't support well different
eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
revision had to be introduced, thus requiring a new Zephyr
driver.
2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
don't use the DMAMUX IP (instead, channel MUX-ing is performed
through an eDMA register in the case of i.MX93).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit updates the driver to use the flash layout pages,
rewriting it to utilize the flash_page_layout.c driver to
avoid duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
This commit adds layput page cells to the atmel sam flash
controller and the flash node. These allow for describing
the actual flash page layout of each soc, allowing the
flash driver to fully utilize the capabilities of the
flash.
With this update, we unlock the following capabilties:
- utilize 2048 erase block size for small sectors
- utilize 16384 erase block size for large sectors
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Change the gpio_qdec driver to support optical encoders.
Add a property to use for defining an arbitrary number of GPIOs for the
sensing devices (typically infrared LEDs, but could also be the
biasing for the phototransistor), and one for adding a delay between
turning those on and reading the pin status.
The infrared LEDs typically consume a non negligible amount of power, so
there's also a new idle-poll-time-us property that enables two possible
modes of operation:
- if idle-poll-time-us is zero (default) the LEDs are enabled all the
time and the driver enters polling mode using the GPIO interrupt as
with mechanical encoders. This is usable for mains powered devices and
has the lowest overhead on the CPU.
- if idle-poll-time-us is non zero, then the driver polls the encoder
all the time, turning on the LEDs just before reading the state and
shutting them off immediately after, but when the encoder is idle it
switches the polling rate to idle-poll-time-us to save power, and only
polls at sample-time-us when some movement is detected.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added new test for `DT_IRQ_LEVEL` and `DT_INST_IRQ_LEVEL`.
Introduced a new `vnd.cpu-intc` compatible so that we have a
root level interrupt controller that acts as level 1
aggregator, and modified `test_intc` to be level 2 aggregator,
updated test of `DT_IRQN(TEST_I2C_BUS)` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The meaning of txpo is was a bit confusing, as it's an enumeration
rather than a pad number. This confusion extended to the atsamd21_xpro
board using the wrong pins.
This commit adds ASCII-art tables that explain the meaning of rxpo
and txpo on different platforms.
Signed-off-by: Tom Rothamel <tom@rothamel.us>
The max size was determined by looking at the ARCH of the cpu. This really
comes from the ip configuration when generated. Add `max-xfer-size`
property to the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This cleans up the instantiation macro. DBG_COUNTER was also removed
as that appears to be unnecessary. This also allows for if it is a
serial target to be configured from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Adding driver for GC9A01A 240x240 based LCD displays.
Should be working with GC9C01 as well (untested).
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct
asserts when a pin is provided. Note that default is 32, correct for eg
FE310.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Change the synchronization of RMC and GGA NMEA messages from a
timeout to matching their UTC timestamps.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add driver for NXP nx20p3483 power path controller that can be used
to control and protect sink and source path of USB-C connector.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add calls to the PPC API that enables and disables the sink and source
paths in the appropriate USB-C stack states.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.
Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.
Note: it is possible to change voltage only for SD/MMC pins on r8a77951
and r8a77961 SoCs.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add definition of the DMIC to the RT5xx devicetree, including all
PDM channels.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Add driver for NXP DMIC peripheral. This peripheral is present on the
iMX RT5xx and iMX RT6xx parts, as well as some LPC SOCs. The following
features are supported:
- up to 2 simultaneous channels of L/R PCM data (4 channels are not
supported due to limitations of the DMA engine)
- individual configuration of gain and filter parameters for each DMIC
channel input
The driver has been tested with up to 4 PCM data streams (2 L/R channels),
as well as the MEMS microphones present on the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Extend api test suite to cover the new devicetree macros. This
includes extending the devicetree overlay with two new bindings:
- GPIO device which is also an interrupt controller
- interrupt holder using interrupts-extended to point to both
existing interrupt controller test_intc, and the newly added
GPIO device
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
add Master Inter-Data Idleness and
Master SS Idleness field. That fields
are integers.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP.
GPIO pinctrl, read/write and interrupt is supported. Runtime mmio
configuration is enabled, so no need for region definition in
mimx9/mmu_region.c
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The wakeup-source is not used by the driver. Most probably this was
inadvertently left when copying the binding from pcf8523 driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Move the nRF comparator devicetree bindings from ADC to sensors, where the
rest of the comparator bindings are placed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add support for M5Stack AtomS3 Lite development board.
The AtomS3 Lite is a smaller version of the AtomS3 that
features only a StatusLED and no LCD display.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
A 1KHz counter is present in the LPC RTC.
Add support for this counter to get better
resolution for certain applications.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
A 1KHz counter is also available inside the NXP LPC RTC
block. Add a binding to support that counter.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit implements `otPlatResetToBootloader` in two ways:
- trigger reset to bootloader using boot mode retention API
- trigger reset to bootloader by triggering GPIO pin (applicable
for nRF52840 Dongle)
Signed-off-by: Maciej Baczmanski <maciej.baczmanski@nordicsemi.no>
Use the common io-channel-cells name "input" instead of "channel" to make
this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is a driver targetting the Bosch BMA 4-series accelerometers. It
has been specifically developed for the BMA422 but should be compatible
with others in that line, excepting the BMA400. Supports key attributes
and async RTIO one-shot operation. I2C operation is supported, with
stubs for a SPI implementation provided for future improvement.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.
At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:
tx_sync_mode = <0>;
rx_sync_mode = <0>;
is the same as not specifying any of the properties,
tx_sync_mode = <1>;
rx_sync_mode = <0>;
is the same as:
tx_sync_mode = <1>;
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some MCU have limitations with GPIO interrupts. Add a polling mode to
the gpio-keys driver to support those cases.
This required a bit of a refactoring of the driver data structure to add
a instance wide data, and move the pin specific pointer in the config
structure.
For polling, reuse the button 0 delayed work so we minimize the resource
waste, the two work handler functions are only referenced when used so
at least those are discarded automatically if no instance needs them.
Fix a bug in the PM structure instantiation as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add an input driver to read data from an analog device, such as a
thumbstick, connected to an ADC channel, and report it as an input
device.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver that based on RPI-PICO's PIO feature for ws2812.
This driver can handle WS2812 or compatible LED strips.
The single PIO node can handle up to 4 strips.
Any pins that can be configured for PIO can be used for strips.
I verified the samples/driver/led_ws2812 sample
working with WS2812(144 pcs) led strip using following patches.
- samples/drivers/led_ws2812/boards/rpi_pico.overlay
```
/ {
aliases {
led-strip = &ws2812;
};
};
&pinctrl {
ws2812_pio0_default: ws2812_pio0_default {
ws2812 {
pinmux = <PIO0_P21>;
};
};
};
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
ws2812: ws2812 {
status = "okay";
output-pin = <21>;
chain-length = <144>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
```
- samples/drivers/led_ws2812/boards/rpi_pico.conf
```
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
